14Mhz Accelerator

[Mathesar]

Originally Posted by Iscord

This circuit has too many problems... I fixed the obvious errors, but it still doesn't work.
I need to find a working one so I can compare the signals with oscilloscope.

Well, you did try
But there is indeed more than one problem in this accelerator.

[Kai]

Just an FYI - this was never once billed as 100% working and ready for use - it's a WIP project that i've put out there - the github exists for people to try it out, test, make changes etc - the whole point of this.

I've had barely any time to do anything electronics related in months, i'm happy to look into the issues here, when i have time.

What won't happen is for me to spring into action when people start slating me for putting this out there.

I already stated that it is NOT my schematic, that it's the livio plos schematic that i've put into KiCAD for all to have a go with.

[DamageX]

Originally Posted by Mathesar

You also need the driver which I modified from the original. I first have to contact the original author to have permission for that.

Hi, I was wondering if you found out anything on the status of this driver. I am also using a modified version for my own A2000 IDE interface. It would be cool if we could redistribute an open source version with improvements, don't you agree? (bootable ROM-resident version would be especially nice)

The original driver has some delay loops that can run too fast on my '030. The sector read/write code also is not ideal for '030 because the unrolled loop thrashes the instruction cache. I got better performance (2.5MB/s) with a small loop and 32-bit MOVEs.

When /IOR or /IOW command lines are delayed a little bit beyond /AS going low, as well as returning high immediately when /AS goes high, timing seems to be agreeable enough for back-to-back reads. See this scope capture: http://www.hyakushiki.net/misc/ide755.png

Top signal is /CS0 (A12), bottom is /IOR

[Mathesar]

Originally Posted by DamageX

Hi, I was wondering if you found out anything on the status of this driver. I am also using a modified version for my own A2000 IDE interface. It would be cool if we could redistribute an open source version with improvements, don't you agree? (bootable ROM-resident version would be especially nice)

The original driver has some delay loops that can run too fast on my '030. The sector read/write code also is not ideal for '030 because the unrolled loop thrashes the instruction cache. I got better performance (2.5MB/s) with a small loop and 32-bit MOVEs.

When /IOR or /IOW command lines are delayed a little bit beyond /AS going low, as well as returning high immediately when /AS goes high, timing seems to be agreeable enough for back-to-back reads. See this scope capture: http://www.hyakushiki.net/misc/ide755.png
Top signal is /CS0 (A12), bottom is /IOR

Hi, and welcome to EAB!
I don't know the license status of this driver. However, i think it is ok to tinker with it. So you have been playing with it as well? I also had to adjust some delays as in my case they were way too long causing hdtoolbox to freeze when scanning the slave drive. I also added some error handling in the driver as that was either non existant or broken. The driver can now reliably detect and/or ignore a slave drive.
I agree about the ior/iow timing. In my version of the hardware I adjusted the timing as you described and indeed 32bit moves work well. See this diagram from my notebook:

Did you use the original hardware or did you also modify it?
Like you I got most performance using a small loop as well but only on an 68010. On the 68000 an unrolled loop worked best. I never tested and 68030.
It would indeed be great if we could make this driver romable and bootable.

[DamageX]

I was confused about how to set it up with hdtoolbox. Currently I am using a mountlist with FAT95 to mount a disk originally formatted on my PC.

I am going through trial and error with the hardware. My test board was designed with a few TTL chips and it had a few address ranges that I could set it to. On the A2000 Zorro slot it was not possible to run $DA0000. I could run it at $80-$900000 but only with the data cache turned off. I assembled a second board with just a PLD hooked up to map it at $EF0000, and fine tuned the timing a bit with the PLD. But like the original A500IDE project, there is no buffering of the data bus, so if I plug in additional Zorro cards then the signal becomes too weak and communication fails.

I'm considering a board redesign with buffering, ROM socket, and autoconfig controlled by a PLD.

Although for A500s without Zorro slots it might be good to replace scsi.device inside the kickstart ROM to make it bootable instead. I'm not sure which is easier.

[PeteAU]

Cute board, I like its simplicity and modest aims. Did this used to work in 1992 and now it's a problem of layout and component selection?

[Mathesar]

Originally Posted by PeteAU

Cute board, I like its simplicity and modest aims. Did this used to work in 1992 and now it's a problem of layout and component selection?

Tempting isn't it?????
I think this kinda worked in 1992... if you used the motherboard 14MHz clock instead of the local doubled clock.
Combine this with Mika's A500ide and you have a nice accelerator/hd combo that anyone can build. No programming tools required!

[PeteAU]

Originally Posted by Mathesar

Tempting isn't it?????
I think this kinda worked in 1992... if you used the motherboard 14MHz clock instead of the local doubled clock.
Combine this with Mika's A500ide and you have a nice accelerator/hd combo that anyone can build. No programming tools required!

Yes, add this to your IDE board. I ebayed a couple MC68HC000FNs

Did Iscord try your idea of changing the caps? Seems like a solvable problem. There is an error in the schematic of connecting CDAC to the R-C delay, but I guess Iscord already fixed that. Using CDAC was meant to be a jumperable option INSTEAD of the R-C delay, is my understanding.

How does this work with fastRAM, it just accesses it at 14 MHz and assumes it'll keep up?

[Hewitson]

Wow, check out that "clock" circuit. Don't waste your time with this board guys, it's a terrible design.

[Mathesar]

Originally Posted by Hewitson

Wow, check out that "clock" circuit. Don't waste your time with this board guys, it's a terrible design.

Nothing that can't be fixed. I have an idea for a better (and still simple!) clock doubler that does work and uses somewhat period-correct parts

[jbilander]

Maybe put a PLL on there or is it too easy?

https://www.diodes.com/assets/Datasheets/PT7C4511.pdf

[Mathesar]

Originally Posted by jbilander

Maybe put a PLL on there or is it too easy?

https://www.diodes.com/assets/Datasheets/PT7C4511.pdf

Naah, too easy But probably even better than this:
https://www.google.com/url?sa=t&rct=...dpoEG39CRzHNY0
This is an old school (period correct) PLL in a DIP package that can run up to 16Mhz or so. But, if you let it run at just 7MHz and use the XOR-type phasedetector, the output of the phasedetector will be a nicely doubled 14MHz clock.

[PeteAU]

Originally Posted by Mathesar

Naah, too easy But probably even better than this:
https://www.google.com/url?sa=t&rct=...dpoEG39CRzHNY0
This is an old school (period correct) PLL in a DIP package that can run up to 16Mhz or so. But, if you let it run at just 7MHz and use the XOR-type phasedetector, the output of the phasedetector will be a nicely doubled 14MHz clock.

If you are going to tinker with this, take care with the Kicad schematic. I think VMA (pin 19 of old 68000 socket) is driven wrongly. It should come out of a 74LS157 mux. IMO I would dump the 157s altogether and just put 5 jumpers, low-tech and smaller

Does your clock idea cater for 21MHz for later?

[Mathesar]

Originally Posted by PeteAU

If you are going to tinker with this, take care with the Kicad schematic. I think VMA (pin 19 of old 68000 socket) is driven wrongly. It should come out of a 74LS157 mux. IMO I would dump the 157s altogether and just put 5 jumpers, low-tech and smaller

Does your clock idea cater for 21MHz for later?

To go beyond 14Mhz would probably be better done by a proper, modern pll.
But for a simple, old school doubler the 4046 would do the job.

[Sim085]

I have gone through the thread and from what I understand two cards are under discussion in this; one presented in the first post and another presented in post 25. The one posted at post 25 can take same cpu format as original on the Amiga. Both cards run at 14MHz, i.e. - CPU must be able to handle this much, i.e. - cannot use the original CPU.

Is the above all correct?

If I have no interest in IDE and FastRAM as I already have a card for that then is the design presented in post 25 usable? Or this too is work in progress?

[MiaM]

Hi!

I'm pretty sure that this is the 14MHz accelerator I did build back in the early 90's.

I used the CDAC signal (or whatever it's called) rather than any analogue delay circuit to generate the the 14MHz clock signal.

I built mine on two lab PCBs. First I soldered a socket för the CPU and a component adapter for the motherboard on one la PCB, together with a pin header. Using jumpers at the apropriate places on the pin header I could run the Amiga at it's usual 7MHz speed, which made me sure that I've soldered this adapter PCB correctly.

Then I soldered all the 74xx logic IC's on another lab PCB and added a short wire which did fit the pin header, and another wire for the CDAC clock. I also soldered a single pin from a pin header on the Amiga main board at some existing solder point (probably a VIA) where the CDAC signal were already available.

Sysinfo stated that it ran at slightly below 12Mhz, which of course isn't true but it's the performance you'd get without any memory fast enough for the CPU speed.

I would suggest that any modern replication of this accelerator might be done the same way, I.E. two separate PCBs or at least jumpers to make it possible to disable the stuff that actually speeds things up. Especially with a PLCC CPU it's hard to check that the CPU itself works without having a working acceleratior.

I would say that the main merits of this accelerator is that it solves the E clock timing and the slowdown needed to run any CPU at a faster speed than the regular 7MHz. It would likely not be much harder to up the speed even further, and likely also not that hard to replace the 68000 with for example a 68020 or 68030. THe 020 and 030 can afaik be used directly with the 16 bit bus of a 68000 system without needing cumbersome buffers to shift data around. Not that there is that much point in making yet another 020/030 accelerator now that we already have the Terrible Fire accelerators. I also don't really know what 68020's and 68030's go for, or for that sake what the faster 68000's and perhaps 68010's go for either. If there isn't much price difference beteween a 020 and a 000 it might be a good idea to go for a 020 directly. It would require some more tinkering as it's no drop-in replacement, but AFAIK you'd only need to decode the signals from the 020/030 saying what data transfer size it want's to do, and also read the A0 line, and create a response to the CPU telling it that the data is on a 16-bit bus, and also generate UDS and LDS to the Amiga motherboard. Don't quote me on this though...

[keithamiga1200]

Has anyone built this card?

[Mathesar]

I like this accelerator a lot. The fact that it uses no programmable logic but just 7400 logic makes it easy to build for everyone.
As the current implementation has some issues I went back Livio's and Jorg's original design. I have drawn out all the waveforms of that design on a piece of paper and to me everything seems sound. The AS/DTACK timing is perfect and the E-clock is almost perfect. So, I think the original design *should* work. However, lacking any fastram the design barely accelerates, just a few percent.
So, I simplified the original design a bit (eliminated the hex inverter), removed the on/off switch, changed the clock doubler and added 1Mbyte of zero waitstate ranger ram. Still using only 7400 logic.
The result is an accelerator with 1MByte of fastram that should be about 2.5 times faster than an A500. I just ordered the boards+parts.
Fingers crossed that it works!
Attachment 71332

[amigasith]

Looks awesome I really look forward to your tests, @Mathesar

[AJCopland]

Nice work Mathesar!

Looks like a really neat little board, I've got a couple of A500's and would love to upgrade one of them just that tiny amount with something like this.