DDFSTRT/DDFSTOP for Hires reverse calculation.

[ross]

Originally Posted by paraj

EDIT: Nice entries guys, still digesting some of it

Yeah, I liked it very much (congrats to you also )

So different from each other!

[malko]

Originally Posted by ross

when you finish it call me, i'll go up too

+1

[meynaf]

Ok, I'm late so it does not really count, but here it goes (56 bytes) :

 moveq #1,d5		; ~fe
 tst.w d2
 bne.s .fe
 and.w d5,d3
 moveq #3,d5		; ~fc
.fe
 or.w d5,d0		; d1-d0 -> b0 (b1) =0
 or.w d5,d1		;

 lsr.w #2,d2		; non-aga : d2.w=0
 bcc.s .naga
 lsr.b #1,d4
 addx.b d2,d2		; ok (d2.b=0)
 lsl.b #8,d4		; -> d4.b=0, x=b0
 addx.b d4,d2		; d2=fetch
.naga

 moveq #3,d4		; 3+large
 sub.w d3,d2		; d2 = d2-d3
 bcs.s .ii		; -> d3=nc / d4=3
 add.w d2,d3		: d3 = d3 + d2-d3 (= d2)
 add.w d2,d4		; d4 = d2-d3 (+3)
.ii
 addq.w #4,d3		; +4

 sub.w d0,d1		; stop-strt
 moveq #1,d0		; d0=pad
 lsl.w d4,d0
 subq.w #1,d0
 add.w d1,d0		; +pad
 lsr.w d4,d0		; d0=blocks
 addq.w #1,d0		; +1
 lsl.w d3,d0
 rts

Too lazy to verify if i didn't break anything. It's too hot to code these days :/
It assumes d0/d1 in range 0000-00ff, perhaps shouldn't.

[a/b]

Originally Posted by meynaf

It assumes d0/d1 in range 0000-00ff, perhaps shouldn't.

Well, it looks like it's do whatever you want. I'm masking top bytes (basically, c code is 0xfc/0xfe, and not 0xfffc/0xfffe), but if that's not needed, I could adjust my code down to 50 bytes ;p.

[ross]

Originally Posted by meynaf

It assumes d0/d1 in range 0000-00ff, perhaps shouldn't.

Originally Posted by a/b

I'm masking top bytes (basically, c code is 0xfc/0xfe, and not 0xfffc/0xfffe)

Thanks meynaf.

Yep, code mask out the bit unused in real DDF registers (like for FMODE).
So no 0000-00ff range
This made the proposed solutions much more interesting.

Originally Posted by a/b

.. but if that's not needed, I could adjust my code down to 50 bytes ;p.

Exaggerated!

[paraj]

Sorry for propagating the 00-ff myth. Couldn't even beat a/b with that doping in my version (it can be fixed w/o increasing size though).

[meynaf]

Originally Posted by ross

Thanks meynaf.

Yep, code mask out the bit unused in real DDF registers (like for FMODE).
So no 0000-00ff range
This made the proposed solutions much more interesting.

Then my 56 becomes 58 (damned not.b d5). Keeping it at 56 would mean stealing code from your version

By the way, the hardware DDF registers have H8 bit, so shouldn't range be 0000-01ff instead ?

Originally Posted by ross

Exaggerated!

I think i've spotted a way to do it in 50 bytes.

[ross]

Originally Posted by meynaf

By the way, the hardware DDF registers have H8 bit, so shouldn't range be 0000-01ff instead ?

Bit in DDF registers are:

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ECS/AGA:
xx xx xx xx xx xx xx xx H8 H7 H6 H5 H4 H3 H2 xx
OCS:
xx xx xx xx xx xx xx xx H8 H7 H6 H5 H4 H3 xx xx

The strange numbering is due to the different internal counter of Agnus and Denise.
Agnus has an 8-bit counter while Denise has a 9-bit counter.
As for other (Denise') registers we have H8/H1 + a separate H0 they thought of doing the same thing..

This way the bit positioning is exactly the same as Agnus internal counter and the hw comparison is straightforward.

[ross]

Actually this is even more 'twisted' in AGA/Lisa where they separated, in some case, the bit differently.
The funniest are the HB registers where the lower bits are in the upper byte:

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
xx xx xx xx xx H2 H1 H0 HA H9 H8 H7 H6 H5 H4 H3

So Alice do a simple mask and Lisa shuffle it.
Notice they changed 'bit names' because of lisa 11 bit counter

With this new numbering AGA DDF registers should be:

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
xx xx xx xx xx xx xx xx HA H9 H8 H7 H6 H5 H4 xx

Nice eh..

[meynaf]

So the doc i have is wrong, as it says :

	BIT# 15  14  13  12  11  10  09  08  07  06  05  04  03  02  01  00
	USE  XX   X   X   X   X   X   X  H8  H7  H6  H5  H4  H3  H2   X

[ross]

Originally Posted by meynaf

So the doc i have is wrong, as it says :

	BIT# 15  14  13  12  11  10  09  08  07  06  05  04  03  02  01  00
	USE  XX   X   X   X   X   X   X  H8  H7  H6  H5  H4  H3  H2   X

To me seems a bad OCR scan that missed some spaces (notice the two xx in upper bit that do not make sense).

[a/b]

Originally Posted by meynaf

I think i've spotted a way to do it in 50 bytes.

Combine Ross' and my versions and you get 50: his first 13 instead of my first 13 (dbcc 2 words), then change fetch from d4 to d5 in my code.

[meynaf]

Originally Posted by a/b

Combine Ross' and my versions and you get 50: his first 13 instead of my first 13 (dbcc 2 words), then change fetch from d4 to d5 in my code.

Yes this is what i had in mind.

[ross]

So, for the annals, the ultimate* version:
*EDITED

fetchWidth:
    add.w   d2,d2       ; separate chipset
    moveq   #0,d5
    subq.b  #4,d2
    bne.b   .0
    lsr.w   #1,d4       ; extract FMODE
    addx.w  d2,d5
    lsr.w   #1,d4
    addx.w  d2,d5
    subq.b  #2,d2
.0  and.w   d2,d0       ; mask DDF
    and.w   d2,d1
    addq.b  #5,d2       ; trick for res mask
    and.b   d2,d3

    moveq   #3,d4       ; large = 3
    sub.w   d3,d5       ; fetch -= res
    ble.b   .1
    add.w   d5,d4       ; large += fetch (=> 3 | 3+fetch-res)
    add.w   d5,d3       ; res   += fetch
.1  addq.w  #4,d3       ; sub = (res += 4) (=> 4+res | 4+fetch)

    sub.w   d1,d0       ; ddfstrt-ddfstop (<= 0), automatic
    asr.w   d4,d0       ;  ceiling for negatives
    neg.w   d0
    addq.w  #1,d0       ; blocks = 1-((ddfstrt-ddfstop)>>large)
    lsl.w   d3,d0       ; width = blocks<<sub
    rts

[a/b]

I have to disagree :P, 48 bytes:

.Begin	moveq	#3,d5		; large = 3
	subq.b	#2,d2		; -2/-1/0 (OCS/ECS/AGA)
	blt.b	.NoAGA

	and.w	d5,d4		; fetch &= 3
	moveq	#1,d2
	subq.b	#2,d4
	addx.b	d2,d4		; fetch = 0/1/1/2

	sub.w	d3,d4		; fetch -= res
	ble.b	.LowFetch
	add.w	d4,d5		; large += fetch (=> 3 | 3+fetch-res)
	add.w	d4,d3		; res   += fetch
.LowFetch
	st	d2		; -1 (AGA)
.NoAGA	add.b	d2,d2		; mask = 0xfc (OCS) | 0xfe (ECS/AGA)
	and.w	d2,d0		; ddfstrt &= mask
	and.w	d2,d1		; ddfstop &= mask

	addq.b	#5,d2		; mask = 1 (OCS) | 3 (ECS/AGA)
	and.w	d2,d3		; res &= mask
	addq.w	#4,d3		; sub = (res += 4) (=> 4+res | 4+fetch)

	sub.w	d1,d0		; ddfstrt-ddfstop (<= 0), automatic
	asr.w	d5,d0		;  ceiling for negatives
	neg.w	d0
	addq.w	#1,d0		; blocks = 1-((ddfstrt-ddfstop)>>large)
	lsl.w	d3,d0		; width = blocks<<sub
	rts
.End
	PRINTV	.End-.Begin

Your chipset-2 opener (I prefer 2x at the end for better d2 flexibility), it looks like it's optimal (couldn't make it less than 50 bytes with the chipset-1 opener), and paraj's AGA fetch calculation (my older version subq/bgt/addq is also 6 bytes but it has a branch, so I find his better).

[ross]

Originally Posted by a/b

Your chipset-2 opener (I prefer 2x at the end for better d2 flexibility), it looks like it's optimal (couldn't make it less than 50 bytes with the chipset-1 opener), and paraj's AGA fetch calculation (my older version subq/bgt/addq is also 6 bytes but it has a branch, so I find his better).

And this close the circle
Wonderful.

Great job a/b!