14 June 2021, 12:11 | #41 | |
son of 68k
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So what do they do exactly ? If all they do is activate the mmu to solve some problem, they won't work on EC. Maybe they turn data burst off ? Then it's no-op, as it's not active at startup (and cpu command can do this anyway). What else ? |
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14 June 2021, 12:20 | #42 | |
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14 June 2021, 13:23 | #43 | |
son of 68k
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14 June 2021, 13:46 | #44 |
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They open the mmu.library, and if that doesn't find an MMU, they activate the TTx registers to set the entire 24bit address domain non-cachable. 32bit ram remains cache-enabled. But see above, EC detection is not fool-proof, you potentially have to insert a "MMU off" in the envarc:MMU-COnfiguration.
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14 June 2021, 13:53 | #45 | |
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Off-topic, but I would like to know: where exactly can I find the 68030.library? I don't think I've ever seen it on any of my systems and I have several 68030's. Sounds like it could be useful. Last edited by roondar; 14 June 2021 at 13:58. |
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14 June 2021, 14:09 | #46 | |
son of 68k
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So either they can't do a thing at all (not even half working MMU that can be used) or they slow the machine down activating the MMU to fix a rare corner case ? All that, taking the risk of a crash due to potentially defective MMU in EC cpu ? Sorry, but this doesn't sound very useful to me. |
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15 June 2021, 01:00 | #47 | |
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Or just avoid code that is sensitive to caching - but that could penalize other systems that have better hardware. To avoid that in the OS you might need duplicate code to handle the broken accelerator cards, potentially slowing down critical sections and wasting ROM space, or separate versions of the OS for different hardware configurations. CPU libraries are used to avoid having multiple OS versions just to handle buggy cards or new CPUs. We don't want to be like the Mac, which wouldn't work if you didn't have the exact OS version with all the correct patches for your model! |
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15 June 2021, 08:24 | #48 | ||
son of 68k
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And when we need to do it, we have CachePostDMA from exec that can take care of it. In fact, perhaps making chipmem not cacheable at first place isn't such the great idea it looks like. The fixes for faulty boards shouldn't alter the working of non faulty ones. Activating the MMU on a 030 does not come for free in terms of performance. |
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15 June 2021, 08:35 | #49 |
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15 June 2021, 08:39 | #50 | |||
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That's all in terms of "which CPU specific issues are there to fix for the 68030", and that is the job of the cpu libraries. The 68040 library is longer since it also has to provide the fpsp package, and the 68060 is even longer since it also includes the isp.
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Getting working bridgeboards and working graphic cards sounds very useful to me. |
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15 June 2021, 09:06 | #51 | ||
son of 68k
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Or tell me what they can do in that case ? Get a line-F exception while trying a pmove to tt0/tt1 ? Quote:
Besides, if these are properly designed there is absolutely no reason for incompatibility with a 030. Original hardware works fine, these should too. |
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15 June 2021, 09:36 | #52 | ||
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Oh, do you think any VGA chip vendor cared about the Amiga, the 68030 and its hardware bugs? The S3Virge, just to name one particular problem, has the interrupt status and interrupt request clear register and the blitter done flag both in a 32-bit aligned 32-bit word. Now what? Sue S3 for not being compatible with a 68030 bug? |
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15 June 2021, 10:01 | #53 | ||
son of 68k
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What you wrote here implies a partial MMU is always there and working. Quote:
Of course a properly written hardware abstraction layer can also avoid this kind of problem. |
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15 June 2021, 10:42 | #54 | |
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Then, I suppose, you better read the 68030UM from Motorola.
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Will you reroute the existing CVision3Ds in the field? Will you rewrite the CyberVision software? |
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15 June 2021, 11:06 | #55 | ||
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https://www.nxp.com/docs/en/referenc.../MC68030UM.pdf https://www.nxp.com/docs/en/referenc...C68EC030UM.pdf Quote:
Patching existing software shouldn't be that hard either. |
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15 June 2021, 11:10 | #56 | |
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Check closer. The TTx registers always exist. They have a different name on the ECs, though the register mapping is exactly identical (obviously).
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Then, who's stopping you? I'm personally not touching third party software I do not own and whose copyright I do not have. |
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15 June 2021, 11:22 | #57 | |
son of 68k
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In the regular manual i don't see anything EC related. So, exact location please. Nobody's stopping me. It's just that it won't happen until i have such a configuration (i.e. probably never). |
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15 June 2021, 12:00 | #58 | |
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What you're looking for are called the Access Control Registers on EC030 - see page 23 (1-12) of this document: https://www.nxp.com/files-static/arc.../M68000PRM.pdf |
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15 June 2021, 12:14 | #59 | |
son of 68k
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Ok, it's an oddity i didn't know of. |
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15 June 2021, 12:45 | #60 |
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Moreover, cartridge to what port? Extension port which only older Amigas have? Amiga 600 and Amiga 1200 have PCMCIA here and... it can be used to put RAM here so no problem to use ROM with small NV-RAM to cartridges (or rather card-ridges? ). But no one made such since A600 and A1200 have IDE controller, and it made cartridge-like media little obsolete.
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