High density floppy for the A1200

[pandy71]

IMO those potentiometers allow only for small adjustment (maybe few, maybe 10 %).

Your earlier post about AC line motors are not for 3.5' drives - i think that all 3.5' use BLDC with proper motor driver - also what is really important - some of those fdd can generate Index pulse based only on FG signal - they don't need any magnet or Hall sensor because they detect state of the magnetic field on flywheel

[Fabie]

Originally Posted by pandy71

IMO those potentiometers allow only for small adjustment (maybe few, maybe 10 %).

Your earlier post about AC line motors are not for 3.5' drives - i think that all 3.5' use BLDC with proper motor driver - also what is really important - some of those fdd can generate Index pulse based only on FG signal - they don't need any magnet or Hall sensor because they detect state of the magnetic field on flywheel

yes...they don't need any hall sensor or magnet to regulate the RPM....seems that hall sensor and magnet are for the pulse

and I will check later if that variable resistors can regulate only a 10%

anyways if the variable resistor regulate a bit....it is possible to change it for another one...or replace it with a common resistor which works at 150 rpm

[pandy71]

Originally Posted by Fabie

yes...they don't need any hall sensor or magnet to regulate the RPM....seems that hall sensor and magnet are for the pulse

Pulse can be generated without Hall sensor or similar solution... at least some motor drivers can generate valid INDEX pulse based only on FG signal feedback (motor driver FAN8422G have such feature for example).

Originally Posted by Fabie

and I will check later if that variable resistors can regulate only a 10%

IMO regulation is only for final adjustment.

Originally Posted by Fabie

anyways if the variable resistor regulate a bit....it is possible to change it for another one...or replace it with a common resistor which works at 150 rpm

I doubt that by changing resistor any half speed regulation can be achieved - add some divider - it is simpler and more reliable than changing resistor.

Also really important is to increase amplification for 150rpm in read amplifier (and maybe reduce write current) - signal is lower and more noisy if floppy revolve with 150rpm.

Fabie - can You made some pictures for IC used on Yours fdd? im collecting information about IC used in floppy drives. Please, TIA

[yaqube]

Originally Posted by whitebird

Does anyone know what's inside the PAL chip? Or at least some principles about the logic?

I modified an EPSON floppy drive to work as Amiga HD drive many years ago. All the required logic was contained in one GAL chip. There was a programmable clock divider (divide by 1 or 2) for clocking the disk motor and the RDY generation logic (drive id). I remember that this programmable clock divider was my first asynchronous FSM design .

I should have sources and jedec files somewhere. When I find them I can post them if anybody is interested in them.

[whitebird]

yaqube, it would be nice from you if you could also explain what the drive modifications are about.

[pandy71]

Originally Posted by yaqube

When I find them I can post them if anybody is interested in them.

As always! Everything what is related to Amiga is interesting! TIA yaqube

[Fabie]

ok

I tried to regulate the variable resistors and doesn't not spin down to 150 rpm
it regulate RPM only a bit...around 3 %...
the variable resistors regulates between 1 and 10k

while.... I dismantled my original A1200 drive
it's a Mitsumi D357T2
this drive looks easy to mod compared to the others I have
so I 'm concentrate in this drive
ok
I found a crystal there
it is in the pic with a red circle
I think the next step is remove that crystal and add the oscillator circuit

if anyone can help with this because I don't understand very much where the oscillator circuit must be connected

thanks

[Khyron]

Originally Posted by yaqube

I modified an EPSON floppy drive to work as Amiga HD drive many years ago. All the required logic was contained in one GAL chip. There was a programmable clock divider (divide by 1 or 2) for clocking the disk motor and the RDY generation logic (drive id). I remember that this programmable clock divider was my first asynchronous FSM design .

I should have sources and jedec files somewhere. When I find them I can post them if anybody is interested in them.

I'm definately interested, it would be nice if you could post the logic & schematics to see how you did it.

[whitebird]

Fabie,

I'm not sure I understand well what you are trying to do. But if you think that you'll be able to change the rotation speed by replacing this crystal with an oscillator, I wouldn't try that. How do you know this crystal regulates rotation speed and is not the drive's MPU clock?

[pandy71]

Crystal produce in internal oscillator (motor driver) frequency - frequency is divided by some fixed ratio and produce frequency used by 3 phase power driver - power driver enable coils that together with magnet in flywheel create rotation - this is simplified basic idea how BLDC engine work - to slow rotation by half frequency used as a reference must be also half of that used for 300rpm. So creating external oscillator + some switchable divider made on additional flip-flop we may chose one of two frequencies - nominal or half ie we can select 300 or 150 rpm

[pandy71]

Originally Posted by Fabie

if anyone can help with this because I don't understand very much where the oscillator circuit must be connected

I need IC type used as a motor driver - this chip visible at the bottom or rather half of it visible - this is probably some BAxxxxx chip from ROHM company.

On datasheet for this chip - pin used for ref frequency can localized.

[Fabie]

Originally Posted by whitebird

Fabie,

I'm not sure I understand well what you are trying to do. But if you think that you'll be able to change the rotation speed by replacing this crystal with an oscillator, I wouldn't try that. How do you know this crystal regulates rotation speed and is not the drive's MPU clock?

I'm not sure if that will works or not
but it is based on the docs in this archive
take a look

[pandy71]

It will work - if fdd have more complex motor driver (ie it is usually bit older fdd not the new one which is usually highly cost reduced with lack of even jumper block to reconfigure drive) there is switch to change speed (300/360/600/720/1200/1440 rpm can be selected e.g. LB1817M IC is capable to switch for those rpm only by using 3 line interface) so change can be made only by selecting proper combination and reducing ref freq by half (ie 300 will be 150 and 600 will be 300 or even further and reduce speed to 75rpm which give us something like 3.52MB fdd ) or with variable clock some variable track capacity can be created - outer tracks more dense, inner tracks less dense

[whitebird]

And what about adding an HD compatible controller to the Amiga? The problem is that compatibility with Amiga disk formats would be lost if it's a standard PC controller.

So the best would be to build a custom controller from an FPGA for example, add Amiga capabilities like those of Paula and make it HD capable.

Anyone know where information about the Amiga FDD controller can be found?

[Jope]

The RKM. Feel free to reimplement Paula in FPGA and have it support full speed HD drives.

[pandy71]

Originally Posted by whitebird

And what about adding an HD compatible controller to the Amiga? The problem is that compatibility with Amiga disk formats would be lost if it's a standard PC controller.

Standard PC controller use something like uPC765 circuit - this is completely different idea behind FDD control - it doesn't fit to Amiga architecture.

Originally Posted by whitebird

So the best would be to build a custom controller from an FPGA for example, add Amiga capabilities like those of Paula and make it HD capable.

So Paula need to support at least 500kbps - it can be made - DMA allocate 3 cycles for FDD - 500kbps should fit.

Originally Posted by whitebird

Anyone know where information about the Amiga FDD controller can be found?

US4780844

[Toni Wilen]

Originally Posted by pandy71

Standard PC controller use something like uPC765 circuit - this is completely different idea behind FDD control - it doesn't fit to Amiga architecture.

So Paula need to support at least 500kbps - it can be made - DMA allocate 3 cycles for FDD - 500kbps should fit.

"Amiga way" is to DMA raw bitstream to/from disk. DD is 500kbps, HD needs 1Mbps. Doublescan screen mode will fix DMA bandwidth issue, only real problem is Paula not understanding 1us (HD) bit cell size.

[pandy71]

btw Toni did that mean that non MFM (like RLL 2,7) coding can be used (for example in Paula GCR mode - is there any description what is difference between MFM and GCR mode in Paula - i know difference betwen MFM and GCR coding but i dont know difference in Paula between GCR and MFM mode)
Probably this is used in gcrdisk.device from HiDensity.lha

[Toni Wilen]

Originally Posted by pandy71

btw Toni did that mean that non MFM (like RLL 2,7) coding can be used (for example in Paula GCR mode - is there any description what is difference between MFM and GCR mode in Paula - i know difference betwen MFM and GCR coding but i dont know difference in Paula between GCR and MFM mode)
Probably this is used in gcrdisk.device from HiDensity.lha

I think so but I have never used or never seen anyone using 4us mode or MSBSYNC bits.. (UAE for example ignores both bits, I havent bothered without any test programs..).

Paula simply writes bit streams, either using 2us or 4us bit cell timing. Paula does not care if it is valid MFM or GCR or whatever.

Reading of course uses PLL (or something similar, afaik it is not fully known how Paula converts pulses from drive to bits), data coming out of PLL is DMAed to memory without any extra processing.

Paula is quite dummy compared to "real" floppy controllers, all decoding and encoding has to be done in software.

[pandy71]

Originally Posted by Toni Wilen

I think so but I have never used or never seen anyone using 4us mode or MSBSYNC bits.. (UAE for example ignores both bits, I havent bothered without any test programs..).

I can imagine - there is no need to create real hardware Paula emulation in software emulator.

Originally Posted by Toni Wilen

Paula simply writes bit streams, either using 2us or 4us bit cell timing. Paula does not care if it is valid MFM or GCR or whatever.

For data OK, but what with synchronization?

Originally Posted by Toni Wilen

Reading of course uses PLL (or something similar, afaik it is not fully known how Paula converts pulses from drive to bits), data coming out of PLL is DMAed to memory without any extra processing.

Paula is quite dummy compared to "real" floppy controllers, all decoding and encoding has to be done in software.

So it was my question - difference between GCR and MFM mode from synchronization point of view - Paula is "dummy" probably due limited resources during developing - i can imagine that they run out of money and time but this give accidentially one of the most flexible FDD "controllers"

THX Toni!