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#161 | |
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I never drew shorter lines or xorred any pixels ![]() |
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#162 | |
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![]() (The two first downloads was with blitter nasty enabled (no bug) i upploaded new version 16.01.13. I now use 5 sprites and 3 dummy attacked sprites (so i can use the same colour as mask). The buggi version use 8 fullsize sprites, 3 attacked). Last edited by Lekman; 17 January 2014 at 23:57. |
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#163 | ||
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#164 |
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Not sure why I have missed this.. (Perhaps I am the the only one..) Probably because my usual test Amiga 500 has ECS Agnus.
DDFSTRT = 0x18 and OCS Agnus: All sprites are disabled. (ECS = sprite 0 is works normally, other sprites are disabled) I checked this condition with logic analyzer and only first sprite word is fetched in this situation, second word fetch slot is not used. It seems OCS Agnus expects idle cycle after both sprite fetches, when DDFSTRT = 0x18, second word is 1 cycle before first bitplane DMA slot. |
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#165 | ||
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#166 |
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Yes, BPLCON1 won't have any effect on DMA usage, it is Denise register.
I finally compared "blue" HRM and "black" HRM DMA time slot allocation page, differences are interesting: Earlier revision says: "cycle $18 or earlier will wipe out all sprites" ... "if SPRITE0 is desired to function then the data fetches cannot begin any earlier than cycle $1c" Later revision says: ..."This allows the user to wipe out most of the sprites if desired (by defining an extra-wide display)".. ECS improvements have separate chapter but it does not mention fixed sprite 0 in max overscan (which is obviously a bug or some chip restriction because there is no DMA cycle conflict even if DDFSTRT=$18. It should have worked in OCS already.) It looks like they didn't really want anyone to notice it ![]() EDIT: I tested all DDFSTRT positions from $18 to $38 with OCS and ECS Agnus. OCS Agnus is always "off by one", DMA slot at DDFSTRT-1 is never used for sprite DMA if OCS (it is available for any other DMA channel or CPU). Last edited by Toni Wilen; 29 January 2014 at 19:04. |
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#167 |
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So a Superfat Agnus should be enough to fix it? From memory it doesn't on a Rev 6A Superfat A500. Which should mean it was in two 1MB Agnus chip revisions at least? See Wikipedia. Would be cool to pin the change down to chip revision, that's the revision that's a true ECS Agnus to me anyway
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#168 | |
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#169 |
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Confirmed. I think it was the 2nd bitplane of unattached 8th sprite missing or not at $30 I was thinking of.
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#170 |
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Hi Photon, I didn't know that bug you are mentioning. so when DDFSTRT = $30 the 2nd plane of the 8th sprite "flickers"? (only if sprite is not attached?)
I think I had seen this happening, but I thought it was a bug in my code ![]() Only on certain Agnuses, I guess Last edited by TheDarkCoder; 31 January 2014 at 18:18. Reason: typo |
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#171 | |
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Quote:
If DDFSTRT is large enough when sprite position information is fetched (POS&CTRL) but DDFSTRT becomes smaller when sprite is displayed, second "plane" of sprite stops getting updated (no DMA fetches) and last fetched data is reused in all following lines. |
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#172 |
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Yes, I don't remember it flickering.
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#173 |
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@Photon: so what do you mean, in your previous post with "8th sprite missing or not". I don't understand :-)
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#174 | |
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I only got the one bitplane showing, but that could be due to the first word in the second bitplane read being zero, and then repeated as Toni says. This raises the question how it has time to even read the first word, since it doesn't even get a DMA slot at any of the following lines. One guess is that it gets latched long beforehand, when the first bitplane DMA word is read at the top of the screen.
In other words, when DDFSTRT is $30, a slot is stolen from a sprite channel by the bitplane DMA starting ealier (more to the left), even though it shouldn't according to (some) documentation. Quote:
Last edited by Photon; 02 February 2014 at 16:45. |
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#175 | |
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Quote:
I think it may even be possible to change the second plane pattern by manually writing to SPRxDATB using CPU. |
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#176 |
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Yes, of course that should work.
From a quick look in HRM you could hope that the bitplane DDFSTRT would steal less sprites in hires or if you're using less than 4 bitplanes in lores. Fetch order is _462_351, so you might even hope less than 2 bitplanes on will fix it. But when I got this I had 1 bitplane on, so that should crush the hope in both cases. |
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#177 | |
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#178 |
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#179 |
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BPLCON1 scaling/zooming
(Partially copied from http://eab.abime.net/showthread.php?t=71437)
How BPLCON1 really works: When Agnus writes to Denise's BPL1DAT, all BPLxDAT registers are copied to internal Denise temp registers and flag is set. (separate flag for both odd and even planes) When bitplane delay value (odd and even are separate) matches Denise's internal hpos counter ((hpos & mask) == delay value) and flag is set, internal temp register is copied to 16-bit output shift register and flag is reset. Hpos comparison checks are continuous, internal copy happens immediately when comparison matches and if flag is set. This explains all weird flickering/blanking side-effects if BPLCON1 values are modified "incorrectly" (comparison does not match before shift register empties too much) mid-scanline. |
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#180 |
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In earlier this thread someone mentioned 7bit ocs mode how colours are defined in this mode? what i know there is only 32 colour registers.
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