First Amiga 600 FPGA Accelerator - Vampire 600

[cpiac64]

my ex mainboard a600?

[majsta]

Yes your board, only one I just can't destroy

[Lord Aga]

Bravo brate, samo napred
Way to go bro, just keep pushing

[majsta]

From now on onboard CPU is disabled and all of this is done by the mini CPU created in VHDL. Complex code 532 lines to reset Amiga motherboard and apply complex 3 wire bus arbitration. [ Show youtube player ]

samo napred odlicno je
go ahead is great

[robinsonb5]

Another breakthrough - exciting stuff!

[majsta]

Next one

[ Show youtube player ]

[majsta]

Accelerator in action, now we have slowest Amiga in the world

[ Show youtube player ]

[Lord Aga]

To care
You da man !

[zipper]

It's a decelerator, not an accelerator

[demolition]

Cool, then you can use it to cheat in games.

[NovaCoder]

Originally Posted by majsta

Accelerator in action, now we have slowest Amiga in the world

[ Show youtube player ]

Cool, well done, always nice to see progress. Can you do an 68060 based one next?

[robinsonb5]

Originally Posted by majsta

Accelerator in action, now we have slowest Amiga in the world

[ Show youtube player ]

That's just awesome! (I have to ask, though, what does Sysinfo's comment on the right hand side say when the machine's slower than a stock A600?)

Once the glitches are ironed out, this thing should have no trouble reaching 40MHz '030 speeds - and maybe more.

[majsta]

It says the same. What can I say, did you believe that could be Phone me now for an snail award hahhahahhah Sorry but I had to...)))

Anyhow to convince myself that all of this is true I had to start FPGA MC68010
So since I have never seen MC68010 in my life I m convinced that concept is working.

[alexh]

2.09MHz eh?

[majsta]

First signs of acceleration... Those are results 2 days ago. Now results are much better but I didn't save any images.

[lukassid]

Can you downgrade A600 to run 1mhz like C64? Hehe
After that only way is up.

[billt]

Originally Posted by majsta

First signs of acceleration... Those are results 2 days ago. Now results are much better but I didn't save any images.

Nice progress since the first success! It's great to see someone not from an engineering background learning how to do this stuff, getting something to work poorly at first and then improving it! I'm very interested to see how far you go with this now.

One thing I noticed on your website:

First of all I didn't include correct version of  SDRAM because I didn't use 16Bit data SDRAM chip to support MC68K data  bus. Instead of that I used SDRAM chip with only 4 I/O's. Why, answer is  simple I didn't have another ones.

It's OK to use a 4 data bit RAM, but I'm curious why you did not use 4 of them in parallel to get 16 total data bits for the 68k bus? Each of the 4 RAM chips then connects identically for address, controls, etc. (for example, ras0 goes from memory controller to ras0 pin of all 4 RAM chips on a single wire, ras1 would be a single wire from memory controller to ras1 of all 4 RAM chips, and so on)

And another question. Now that you have things working as a basic design, do you plan to pick up the enhanced TG68.c design, or N050 after that is (allegedly to be) released as GPL too?
http://minimig.net/viewtopic.php?f=9&t=558 (about halfway down first page is a zip file attachment to a post)

[majsta]

As I told before I m not an engineer I m only technician and went only 4 years to high school but it was 4 years about digital electronics and I left that world 10 years ago, and become professor of something else. All of this I learned in school and practice in few electronics companies back then so it is not completely true that I don't have experience in electronics. I just needed to remember few things

Regarding your questions...

I already included new TG68 design I m refreshing every forum 100 of times per day and it is hard to miss something Problem with SDRAM and other parts I need to keep board in 100x100 size and it needs to be 2 layer board so there is no space. I have managed to run SDRAM at 100Mhz and complete core runs now at that speed. Main problem here now is metastability but I just now in process of solving that. I have an brilliant idea about phase shifting so we will see. I think I will be able to precisely tweak read and write cycles. You must understand that without work on some people and their codes on the web any of this wouldn't be possible. I don't want to state their names because as you can see on some forums I had problems about that. another thing regarding SDRAM I already have 16 bit SDRAM's and they are rated for speed and capacity but let that be surprise, they cost me arm and a leg PCB is going to new redesign because I m now able to remove much components from the board, I don't need so much CLK signals from the board because I replaced them with only 2.

[Loedown]

For what you know and what you have done I take my hat off to you, well done. Good work also for the others that helped and supported.