Zorro III Bus Specifications wanted

[mboehmer_e3b]

Originally Posted by alexh

I take it there was no 16-bit or 8-bit mode interface mode for the USB host controller? There sometimes are. I guess non that were practical or you would have used it in that mode.

Speed. There is a reason for DENEB being the fastest Zorro III USB 2.0 controller on the Amiga - it even beats PCI cards in speed, and runs at low CPU load due to full DMA support.

Heck, why should I do a full 32bit design and bottleneck it by 16bit data pathes inbetween?

Michael

[mboehmer_e3b]

Originally Posted by tnt23

I wish I could use a dedicated ground plane, but four layer PCB would be far too expensive for test project like this I am trying to compensate this with copper power/ground polygons wherever possible.

If you want to go for speed on Zorro III you will need proper GND/VCC planes.
For slow cards it is not of concern, but fast switching signals on a programmable logic IC will make this mandatory.
For "playing around" a two layer PCB is nice, but may cause more problems than it solves (very first DENEB prototype was a two layer card...).

All fast Zorro III cards (gfx cards, SCSI cards, etc.) use four layer PCBs (with few exceptions mainly from Poland), as requested by the Zorro III specs from Dave Haynie, and for technical reasons already mentioned.

You also mentioned that you plan to make matched impedance on the drivers in FPGA to match the board impedance - without GND plane you have no reference plane to calculate the impedance on the PCB at all...

On speed of Zorro III: my old calculations posted here are rule of thumb, it depends on some factors in the system, like CPU card and type, and the bus interface design.
On your 40MB/s assumption... well, dream on. Same for Multi Transfer Cycles - using them is tricky at least, but there is a reason why the DENEB has no support for them (though we played around with that feature during development, so enjoy the game ).

DMA... well. Makes sense for I/O cards with high data load (SCSI like Fastlane Z3 and A4091 or USB2 like DENEB). I don't know of any other Zorro III DMA card. And there is also reason for that... it's complex due to Buster "features", available in Buster 9 and 11. Without playing some tricks you won't get stable DMA on Zorro III.
Nevertheless, DMA on a RAM card is useless. The CPU stores data in RAM, so what would be the benefit for CPU to set up a DMA transfer from your Zorro III RAM card to ... some other RAM, wait for completion of transfer and finally access the copied RAM content by PIO again?

Michael

[alexh]

Originally Posted by mboehmer_e3b

why should I do a full 32bit design and bottleneck it by 16bit data pathes inbetween?

You are the man, and you did the design. I don't claim to know the challenges involved but I regularly down-size buses in my FPGA work to save pins without compromising speed by just running them at twice the speed. This must not have been an option of your USB host controller, otherwise you would I am sure have done so.

[tnt23]

Originally Posted by mboehmer_e3b

If you want to go for speed on Zorro III you will need proper GND/VCC planes.
For slow cards it is not of concern, but fast switching signals on a programmable logic IC will make this mandatory.
For "playing around" a two layer PCB is nice, but may cause more problems than it solves (very first DENEB prototype was a two layer card...).

All fast Zorro III cards (gfx cards, SCSI cards, etc.) use four layer PCBs (with few exceptions mainly from Poland), as requested by the Zorro III specs from Dave Haynie, and for technical reasons already mentioned.

You also mentioned that you plan to make matched impedance on the drivers in FPGA to match the board impedance - without GND plane you have no reference plane to calculate the impedance on the PCB at all...

I do not object having dedicated power and ground planes. Even more, I will gladly go for separate PLL power/ground domains as the Cyclone II datasheet recommends. It is just that my board is a prototype, and can thus be excused for not being a four-layered one.

On speed of Zorro III: my old calculations posted here are rule of thumb, it depends on some factors in the system, like CPU card and type, and the bus interface design.
On your 40MB/s assumption... well, dream on. Same for Multi Transfer Cycles - using them is tricky at least, but there is a reason why the DENEB has no support for them (though we played around with that feature during development, so enjoy the game ).

In fact, I was just thinking out loud I didn't mean 40MB/s can be easily achieved, but rather that the sustained data rate on Zorro III could not be more than that. I've dug some information about 20MB/s reportedly done by Haynie's designed SRAM card which could be seen as some reachable goal.

Anyway, I am having a great fun with the project. Trying to support MTCs will be fun, too

DMA... well. Makes sense for I/O cards with high data load (SCSI like Fastlane Z3 and A4091 or USB2 like DENEB). I don't know of any other Zorro III DMA card. And there is also reason for that... it's complex due to Buster "features", available in Buster 9 and 11. Without playing some tricks you won't get stable DMA on Zorro III.
Nevertheless, DMA on a RAM card is useless. The CPU stores data in RAM, so what would be the benefit for CPU to set up a DMA transfer from your Zorro III RAM card to ... some other RAM, wait for completion of transfer and finally access the copied RAM content by PIO again?

Michael

Again, I was just thinking out loud with DMA When reading the specs, you run across things like DMA, or short cycles, or anything else which makes you wonder if it could be useful.

[tnt23]

Okay, so I've got some results
There are still issues with the system not recognizing the memory on startup (I suspect wrong addressing, or byte swap, or other bugs of all sorts). But the memory responds, can be written to and read from. The nice small memtest program helped me a lot in debugging:



Unfortunately it doesn't use patterns like 0x12345678, and won't detect faulty addressing.

And there are the bustest utility results for SDRAM running at 133MHz.



The memory chip was desoldered from a PC100 DIMM. It is a Micron 8Mx16 SDRAM, and can do 133MHz according to the datasheet. However, the memtest reported errors, and I had to lower its clock to 100MHz to run more or less stable. The performance goes down a bit, with peaks at around 9MB/s.

[alexh]

This is your first stab at Zorro III. I'm sure you'll pull in a few cycles here and there and get it faster.

Is it possible to tune the SDRAM pins? Add configurable delays etc?

[tnt23]

Originally Posted by alexh

This is your first stab at Zorro III. I'm sure you'll pull in a few cycles here and there and get it faster.

Is it possible to tune the SDRAM pins? Add configurable delays etc?

The SDRAM controller has been largely vandalized and wounded to fit. Throwing away wishbone rudiments will most definitely help cleaning the design, and indeed could redeem a couple of cycles. Perhaps bringing own controller code will be better.

All configuration, like Autoconfig values or memory latency, is currently compiled in. I think it is quite possible to make it configurable through some linked I/O board and a simple, yet non-existing utility. There are still plenty LEs in FPGA for that.

[alexh]

In our last ASIC all the SDRAM pins all have individual configurable delay lines in them and a method of calibrating this delay so the lengths of the tracks between the RAM and the chip can vary across the PCB without causing too much skew.

[Eriond]

The discussion about Manufacturer IDs never seamed to come to an end... Is there still an official maintained list of IDs?
I would need one, but don't really feel comfortable picking one at random.
Any suggestions?

/Eriond

[tnt23]

Originally Posted by alexh

In our last ASIC all the SDRAM pins all have individual configurable delay lines in them and a method of calibrating this delay so the lengths of the tracks between the RAM and the chip can vary across the PCB without causing too much skew.

No, I didn't go that far with configuring individual pins controlling SDRAM. It has been mentioned that some (but not all) Cyclone II pins have selectable On-Chip Termination resistors (25 to 50 ohm), and also programmable current (from 4mA to 24mA). I think I've also seen something related to configurable delay for certain pins but will have to inspect the topic in more detail.

[mboehmer_e3b]

Originally Posted by Eriond

Is there still an official maintained list of IDs?
I would need one, but don't really feel comfortable picking one at random.
Any suggestions?

Email Olaf Barthel, he's keeping track of the IDs and can assign one AFAIK.
At least I got mine from him in 2005.

That should be the official way.

Michael

[mboehmer_e3b]

Originally Posted by FrenchShark

I suggest you use a multiple of the ZIII frequency as the SDRAM clock.

Zorro III is fully asynchronous and has no clock at all (except E7M only used for bus mastering signal timing).

Michael

[mboehmer_e3b]

Originally Posted by alexh

You are the man, and you did the design. I don't claim to know the challenges involved but I regularly down-size buses in my FPGA work to save pins without compromising speed by just running them at twice the speed. This must not have been an option of your USB host controller, otherwise you would I am sure have done so.

Inside the FPGA - yes, but as soon as you go off-silicon you get slow (as you know, being in ASIC and FPGA business :-) )
For DENEB, this would have saved 16pins, which is not sufficient for SDRAM at all, even if you share the data bus with the I/O controller.

Another thing being "ugly" when sharing an I/O card (like USB) with system memory on the same physical Zorro card: if the I/O can do DMA, what will you do when the system assigns a DMA transfer source/target on the memory on the same physical card? This complicates things, as "normal" Zorro III DMA is not possible any more, and you need to differentiate between "normal" DMA and card internal DMA...
As soon as you are on two Zorro cards, things are easy (in terms of Zorro III) again.

Never measured the speed a DENEB doing DMA can reach with a Zorro III RAM card - in principle the cycles could be shorter than Buster ones, as DENEB operates at much higher frequencies internally and therefore can close Zorro cycles much faster.

Michael

[tnt23]

Another busspeed screenshot:

[chiark]

I'm amazed that write is faster than read... But that's endemic across the system!

[Paul_s]

It's like looking at a blackboard with Einstein's theories on.

[DarrenHD]

Originally Posted by mboehmer_e3b

Zorro III is fully asynchronous and has no clock at all (except E7M only used for bus mastering signal timing).

Michael

I read in Dave Haynie's Zorro 3 notes that the bus master drives the overall speed and the maximum theoretical speed is 50MB/sec.

Of course in practice Z3 doesn't achieve anything close to this, as you have found out.

Anyway, I am keenly interested in a Zorro 3 memory expansion board as my Cyberstorm PPC is hobbled with 128MB ram, maximum, which really sucks for OS4.

I understand any Z3 memory would be slow, but at this point slow memory is better than no memory.

I also understand I will have to convince Thomas Frieden to add support for this memory board, but he is more likely to do it if actual hardware exists and can either be lent to him or him provided exactly what he needs to add to the OS4 kernel to make it work.

[wawa]

is that the third part of busspeed on addr 40000000 thats relevant to your z3 memory, right? seems within anticipated transfer speed. cool that it works already anyway, not very usual among amiga developments. lol.

[alexh]

Originally Posted by DarrenHD

Anyway, I am keenly interested in a Zorro 3 memory expansion board as my Cyberstorm PPC is hobbled with 128MB ram, maximum, which really sucks for OS4.

Pretty sure that Zorro RAM cards can never be use as main memory in OS4. I believe it is just the way it (the existing Kernel?) works. This is why there is no support for DKB3128, Fastlane etc.

[DarrenHD]

Originally Posted by alexh

Pretty sure that Zorro RAM cards can never be use as main memory in OS4. I believe it is just the way it (the existing Kernel?) works. This is why there is no support for DKB3128, Fastlane etc.

Which is why Thomas would have to add support for it.