02 November 2015, 10:50 | #81 |
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I have a micro a1 and seldom use it. I use FS-UAE more than any Amiga. If software is written for 68k I am more likely to use it. Why? PPC code is 30% bigger and slower per byte and per clock cycle. A 68k clocked at 600 MHz will wipe the floor with the 800 MHz A1. FPGA wins. An improved AGA core in an FPGA will do better yet.
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02 November 2015, 13:42 | #82 |
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If 500 Euro was expensive, I assume this will cost 300?
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02 November 2015, 14:15 | #83 |
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I assume you mean Windows? Not capitalized it doesn't make much sense. :P
But you are incorrect, a PC is a computer with a standardized architecture and have never been exclusively used with Microsoft products. Or even limited to x86 processors - the PReP standard was essentially a PC with a PPC processor and the CHRP was also largely based on the PC standard. |
02 November 2015, 14:21 | #84 |
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02 November 2015, 14:51 | #85 | |
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But what is the cost of a Stratix 10 FPGA? Probably $7000+ for small quantities. Or one could take an expensive high-performance Intel chip like a i7 6700K 4GHz (4.2 "turbo", overclockable) ~$400+motherboard+graphics etc. Assuming one can emulate a 68k at 1/4 the native performance one will get a virtual 1GHz 68k processor... |
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02 November 2015, 16:31 | #86 | |
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Also, 1/4 native perfomance on an i7 sounds ambitious, especially since each core of an i7 is dual-threaded making the single-threaded speed roughly half that of the core. |
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02 November 2015, 19:36 | #87 |
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AFAIK Hardcopy is a structured ASIC so it should be approximately as expensive as an ASIC.
And you understanding of "Hyperthreading" (the Intel term - marketing garbage) A.K.A. SMT/Simultaneous Multi-Threading is wrong. If one run one thread on a core it will reach 100% of the performance, if one runs two threads one often get 85%+ per thread. SMT is a way to make use of stall cycles, not a way to execute two threads with barrel processing. |
02 November 2015, 20:44 | #88 |
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Ah, well, HardCopy is discontinued as a product anyway. It used to be possible to get a HardCopy chip in smaller quantities without paying as much due to decreased design cost.
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02 November 2015, 21:56 | #90 |
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Ah, you got to play with Mjölnir for a bit
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03 November 2015, 14:49 | #91 | |
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Perhaps eASIC could be an alternative? Don't know how easy it is to port from Altera. http://www.easic.com/ |
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03 November 2015, 15:13 | #92 | |
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03 November 2015, 15:17 | #93 |
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03 November 2015, 19:44 | #94 |
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I guessing that you are referring to Intel? If so you should brush up on microprocessor history. Calculator processors? LOL!
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03 November 2015, 19:54 | #95 | |
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That was what TI and Intel initially produced. And IBMs choice of the 8088 was particularly pathetic for a costly machine. That gave the system an 8 bit data path to memory, whereas the 8086 at only slightly more cost would have given a 16 bit data path to memory. Don't presume to lecture me about microprocessors, I was using computers before the microprocessor existed. My first personal computer was a hand built SWTPC system, and in the '80s and '90s I worked for a company that designed and built 68K based multitasking multiuser systems. In laughing out loud, you are only making a fool of yourself. And I have no time for fools. |
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04 November 2015, 13:01 | #96 | |
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Beating an ASIC with an FPGA is difficult. I estimated that a 500-600 MHz core based on 68k would be enough to wipe the floor with my PPC 750FX at 800 MHz due to RISC core inefficiency associated with the Load/Store architecture. Since the PPC doesn't use opcode fusion like the Apollo core, the FPGA might catch up with lower clock speeds than even 400 MHz! Using a modular eASIC-style ASIC could get the speed up to what we need if the demand is high enough. Some obstacles are that the core has to be debugged first. Also, since the Apollo core drops some 68k functions that are not legal to use on the Amiga chipset systems, the chip would need to be an SoC with its AGA++ core integrated to make the expense worthwhile of doing the die layout. (The reason I think that is the case is because the Apollo core is only user-mode ISA compatible with 68k. There are other 68k systems that it won't work with.) IF that all happens, it'll be interesting to see how it stacks up against the PPC and more importantly, how well the AGA++ core can mop the floor with an older Radeon card. My MicroA1 has a Radeon 7000 chip on the motherboard and it isn't upgradable. (If the AGA++ graphics core can go far enough to compete with my sister's old Radeon X700, I'll probably ditch PPC for good! The PPC already can't keep up with my Core2 Duo-based Mac.) |
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04 November 2015, 14:56 | #97 | |||
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The 8008*, the 8080 and the 8085 preceded it. They were all general purpose and all generally not used for calculators. At this time there were already specialized calculator chips available that cost less and consumed less power. (* it's probably this one you call a calculator processor however it was designed originally as a terminal controller) Quote:
The 68000 in comparison was used for high-end expensive computers as it was considerably more expensive in every way. Quote:
I found the idea of Intel being called a calculator processor manufacturer funny, is that enough to make me a fool? Well then I'm a fool! LOL! |
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04 November 2015, 17:49 | #98 | |
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And yes, I was specifically thinking of the 4004 (which the 8088 IS descended from). So referring to them as calculator processors isn't that far off base. And what really bugged me was the marketing of these as full 16 bit processors when they are 8/16 bit processors. Also at 4.77 MHz the 8088 is outperformed by a 6809 of less than half its speed (if we want to compare processors from the same era). So no, I wasn't really happy with Intel until the '386 was introduced. It finally had the features needed to port some on the software that I was already using on Motorola processors. Of course today's X64 processors bear little resemblance to their progenitors, so I'm not one of the "let's just build a really fast 68K" fanatics. Although, I still mix in AMD processors whenever they will suffice (its always nice to support the underdog). AND my primary Blender/CAD machine is Intel based (dual Xeon). |
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04 November 2015, 19:48 | #99 | |||
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1) Is the Apollo core in an FPGA or in a real ASIC? 2) Does the Apollo core have a good compiler and instruction scheduler? 3) What kind of caches and memory are used? 4) What kind of algorithms are used? I believe an FPGA Apollo core could outperform, at the same clock speed, most Thumb 2 ARM processors (where power efficiency is more important than performance) in single core performance. PPC is generally stronger but ARM has been closing the gap with deeper pipelines, OoO and recently a new ISA. The G3 PPC processors are old, simple and power efficient shallow pipeline designs (limits clock speed) but do have some advanced features like reservation stations and large caches (needed for PPC performance). The Apollo core in FPGA could retire more integer instructions per cycle, would be considerably faster per cycle at multiply and would not suffer from RISC load/store bubbles but a good compiler with instruction scheduler is still imperative to take advantage of the 3 integer units and 3 op code fusion without OoO. Quote:
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Last edited by matthey; 04 November 2015 at 19:53. |
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05 November 2015, 11:33 | #100 | |
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