25 May 2024, 14:14 | #81 |
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If the numbers are correct, it's an even bigger shame that Akiko can't do direct DMA to chip ram.
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25 May 2024, 14:18 | #82 | |
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The numbers do look a bit startling though. Especially given that its pixels converted per second, full round trip. I'll put the code on GitHub later in the interests of transparency |
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25 May 2024, 15:16 | #83 |
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The numbers do seem a bit "unpossible" though. This has to be some sort of cache interference if the loop counts are correct and timing is accurate.
I'll move onto testing and actual block conversion when I get a minute later. That might be more informative |
25 May 2024, 18:14 | #84 |
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Haven't spotted any errors in your code, but they seem too good to be true. Unless my math is off (wouldn't be the first time) 53768 CIA ticks would correspond to 20*53768=1075360 14MHz clock ticks with each loop iteration taking (20*53768)/100000 = 10.7536 of those. Seems suspiciously low with 16 accesses... The ones taking twice as long might be believable.
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25 May 2024, 18:39 | #85 | |
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25 May 2024, 20:40 | #86 |
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There's definitely something weird going on with the timing here.
Just out of curiosity I ran the test on the Minimig FPGA core and watched its operation using SignalTap - here's a trace. (There are two accesses per longword because the TG68 CPU has a 16-bit bus, so my implementation of the Akiko cornerturn expects pairs of word accesses.) So a complete iteration, from the start of the first write to the start of the next block of writes, takes roughly 352 cycles of the fastest clock in the system, which is 113.34MHz. I make that 8.82ns per cycle times 352 cycles = 3105ns, or 3.105us for one complete round of the test. The test is 100000 rounds long, so roughly 310.5ms for the entire test. Yet the program usually reports about 89000 ticks, 126ms - and sometimes reports only 2,000 ticks, 30ms. (I'm wondering if maybe ReadEClock() reacts badly to interrupts being disabled for an extended period?) |
25 May 2024, 20:55 | #87 |
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FWIW here's my timing code that I've never had problems with on my 060 (note: hard coded assumption about 50MHz). Can't remember why I open util.library in the code though..
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25 May 2024, 21:26 | #88 |
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To my knowledge, the Eclock is driven by a divider on the bus. It shouldn't be impacted by interrupt status (unless using it to create a delay of course).
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25 May 2024, 21:40 | #89 |
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I don't remember exactly how the OS handles it, but there is the issue of rollover. Can't remember the details right now of how often that happens, but when timing I found it best to let OS do its stuff regularly and sum time time (with DMA off!) of inner loop.
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25 May 2024, 22:48 | #90 |
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Should be about every 101 minutes to wrap the lower 32-bit value at 709kHz or so.
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25 May 2024, 23:05 | #91 | |
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It might be better to time using the TOD clocks - they're 24-bits wide and on slower clocks (VSync or PSU tick for one CIA, and HSync for the other), so wraparound is rare. |
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25 May 2024, 23:07 | #92 | |
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25 May 2024, 23:07 | #93 | |
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EDIT: what robinsonb5 said |
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25 May 2024, 23:12 | #94 |
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That's the first time the Eclock has ever let me down. Mind you, I don't normally write code that runs with interrupts disabled.
A better iteration might be 2560 (equivalent to 320*256 pixels) and accumulate a bunch of those. Then, outliers an be identified and eliminated, and the remainder averaged. Last edited by Karlos; 25 May 2024 at 23:19. |
25 May 2024, 23:17 | #95 | |
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My timing.c spaces the beatings for this reason. |
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26 May 2024, 00:42 | #96 |
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26 May 2024, 00:45 | #97 | |
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learning new stuff all the time
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26 May 2024, 14:13 | #98 |
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Can we retry the version from here:
https://github.com/0xABADCAFE/akiko-fun/tree/main This does 20 runs of 2560x32 e,g, (320x256) and derives from there. Note that it's still only testing reg > hw > reg until we are getting sensible measurements. Then I will start doing actual c2p conversion tests. |
26 May 2024, 15:44 | #99 | |
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Last edited by Lunda; 08 July 2024 at 14:46. |
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26 May 2024, 16:04 | #100 |
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that is more believable.
still almost 9mb/s ain't too shabby. @Lunda is that with the 030 clock at 70mhz? (5 times the 14mhz cpu clock) |
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