07 February 2010, 18:02 | #61 |
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I don't quite catch the idea, why would one clone Buster?
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07 February 2010, 18:31 | #62 | |
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@tnt23:
http://www.a1k.org/forum/showpost.ph...1&postcount=18 under this link calculates m. boehmer, author of the deneb zorro usb-card the maximal theoretical throughtput of z3 bus. Quote:
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07 February 2010, 18:42 | #63 |
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PicassoIV 10-11 MB/s, CV64 is probaly the fastest on Zorro, 16-18 MB/s IIRC. Theoretical max should equal PCI but it's theory...
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07 February 2010, 20:11 | #64 |
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picasso is considered quite compatible for what i ve heard, probably just working along the z3 specs it reaches maximal throughput. cv64 must be pulling some tricks to get that result. i do not know what tricks, yet less i would understand, but i recall it is being considered a problem source by individual computers and e3b. i could provide some hints by them if i wíll find a while to do that.
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07 February 2010, 20:16 | #65 |
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Agreed,it is impressive! As is your work. Will it be zorro II compatible? Do you have any plans to release the layout? Which FPGA have you chosen?
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07 February 2010, 21:30 | #66 | |
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Quote:
The FPGA is 208-pin QFP chip from Cyclone II family. It is not 5v tolerant, hence the Quickswitches. Releasing the PCB layout is quite possible. I doubt it will be of great interest as it only supports one memory chip (and hasn't been verified against all sorts of errors and mistakes). |
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07 February 2010, 22:39 | #67 | |
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Quote:
I put a good five or six hours into the reverse engineering process on my A3000D last night, using a BugKatcher, which is an 84-pin PLCC device that plugs into a PLCC sockets and gives easy access to all of the pins for diagnostic purposes. Here's a photo of my Buster in the bugKatcher: High-res photo of the same thing is viewable at http://farm5.static.flickr.com/4071/...8bfb7819_b.jpg |
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08 February 2010, 01:08 | #68 | |
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Quote:
( i mean at least there is a proof that it fits) |
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09 February 2010, 01:11 | #69 |
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Usually, by the time a hardware hacker decides to spend the dosh to have a professional PCB made, they are pretty sure they have a good chance of getting it working.
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09 February 2010, 09:49 | #70 | |
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Quote:
[ Show youtube player ] |
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09 February 2010, 15:23 | #71 |
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09 February 2010, 15:49 | #72 |
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Plug it in Let out the Magic Smoke.
Nice job, you seem committed to producing something which is very cool. |
09 February 2010, 22:25 | #73 | |
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Quote:
This PCB was intended to be a test board, so it can carry only one SDRAM chip. I was going to use the same memory IC that Altera's DE1 development board has, 8 megabytes in 16-bit words. Address lines should allow for bigger memory organizations, like 16, 32 and 64 megabyte chips. More chip selects can be added later, as well as another memory chip. There are also 7 free GPIO pins available as a 2.54mm header strip, can be used for debugging or something else. |
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09 February 2010, 23:38 | #74 |
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10 February 2010, 05:24 | #75 | |||
FPGAmiga rulez!
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Quote:
Welcome to the world of FPGAs and SDRAMs. The toughest part in the development is using TimeQuest and getting the external I/Os timings right. If you need some help on that part, just PM me. Regards, Frederic Quote:
I prefer spending more time reading datasheets and double-checking the layout than pulling my hair on a non-working PCB. I also check all the voltage rails before soldering the expensive components. Regards, Frederic Quote:
Regards, Frederic Last edited by Graham Humphrey; 10 February 2010 at 07:55. Reason: Back-to-back posts merged |
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10 February 2010, 08:00 | #76 |
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10 February 2010, 08:15 | #77 | |||
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Quote:
Quote:
Quote:
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10 February 2010, 12:06 | #78 |
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Yep. Spent about a week working on the first layout of my IDE controller, and found about a dozen mistakes/improvements after it was made.
Still, you are right, you do need to eventually settle on something, or it will never get done. |
10 February 2010, 15:55 | #79 |
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11 February 2010, 02:15 | #80 |
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You've glossed over the lack of series resistors on the proto board.
The series resistors are almost certainly there to reduce the slew rate (and therefore, the the over- and under-shoot) of the I/O lines. You want to be real careful about this, since the Cyclone devices have very specific tolerances about how much over and undershoot they can take without degrading/dying, discussed in the data sheets. Directly related to this, is the fact that Zorro 2/3 was never conceived with operating with the kinds of slew rates these FPGAs will put out. So, you may wish to check on over/undershoot on the Zorro bus as well, even though you have quickswitches there. |
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