18 August 2021, 14:52 | #41 | |
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18 August 2021, 16:04 | #42 |
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Also, the accelerar always runs @14Mhz. However, when it accesses the Amiga bus the cpu is slowed down so much tools that like Sysinfo will report a slower clock speed.
Last edited by Mathesar; 18 August 2021 at 18:21. |
18 August 2021, 18:25 | #43 |
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If you disable fast RAM it doesnt boot at all - the A590 fails to work in PIO mode with your board. LIV2 took a look an thinks its related to the AS7 and AS. I will take a look later, he suggested adding an AND or NAND there to solve that problem, but I've not had time to look in detail.
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18 August 2021, 21:16 | #44 | |
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19 August 2021, 21:16 | #45 |
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No, it seems the video goes just as the LED flickers on the A590, when RAM is disabled on the A590. Maybe I need to "tune" that resistor you mention in the design.
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19 August 2021, 23:26 | #46 | |
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I don't know of any DMA peripherals/drivers that detects un-DMA:able memory, but please correct me if I am mistaken. It could of course be fixed by setting the mask to only allow transfers to/from chipmem for all partitions (0x1FFFFE). However, it is rather user-unfriendly and it will be extremely slow as buffers allocated by software will always be in highest priority ram - fastram, so the filesystem fixes the transfer by showing them via chipmem in very small blocks. Some drivers will also do pio on such small blocks to make it even worse speed wise then . |
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20 August 2021, 10:36 | #47 |
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Well, C00000 ram is normally not dma-able, and since this accelerator relies on the OS adding it (thinking it is regular slowram), it will get marked non-dma. Also, an A500 doesn't have anything on the mobo supporting dma, it all happens inside the A590.
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20 August 2021, 14:18 | #48 | |||
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Last edited by Mathesar; 20 August 2021 at 14:49. |
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20 August 2021, 17:15 | #49 | |
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The chipset is actually able to "dma" to trapdoor C00000 ram, it just appears to it as chipram (if you have a 1MB+ agnus). |
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20 August 2021, 21:39 | #50 |
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I have raised an issue on GitHub. One thing I just now realize is that this design does not tristate the AS signal when the 68000 grants bus access. This inhibits any DMA transactions on the 68000 bus. So, even DMA transactions between the A590 ram and the SCSI chip will fail. Basically this accelerator does not support DMA controllers.
Could you do another test? Try setting the mask to 0x000000 for all partitions. This will hopefully prevent the driver from doing any DMA at all. It will be slow but if it works it can help us pinpoint the exact problem. |
21 August 2021, 12:16 | #51 |
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The A590 works with the entire 24 bit memory range, if the logic in the accelerator is wired correctly. With my CPLD based 68000 accelerator, I can use every bit of memory range not used by the mainboard, together with the A590. Regarding the local C0 memory access, it is important that Gary is not aware of it while accessed by the A590, as you said; you need to pull down the OVR then, but it will require a wire out of the board. And
you also need to supply a 7MHz synced DTACK as well to the A590 for C0 accesses, since Gary is not providing it in this scenario. If you move the fast-ram over to the Z2 area, it will have to be added during boot, but then some stuff will go into chip-ram before you are able to do so, both slowing down the system and eating precious chip-ram. |
21 August 2021, 12:32 | #52 |
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Correct, the A590 (or other peripherals for the 68000 bus) should be able to access everything the 68000 CPU can, when they are mastering the bus.
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21 August 2021, 15:43 | #53 |
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Let me think aloud here. First thing to change is to make AS7 a tristate signal when another busmaster is active. Easy in a CPLD but on this design it would mean an extra (tristate) buffer gate. Or make it an open collector output, that would require just a schottky diode... (bat54?). What do you think of that? In the spirit of keeping things simple...
Second thing to fix is to feed AS7 (when driven by an external bus master) into the ram controller. That one could be easy I think. We can just feed AS7 into pin 10 of gate U8C. Done! Third thing to fix is to prevent Gary from interfering.... Without any additional logic the ram could be moved to $300000, $500000, $600000 or $900000. So, with a bit of luck it could be fixed with just some rewiring and the addition of a diode and a pullup. Any things I'm overlooking? See here for the current schematic: https://github.com/Mathesar/14mhz-ac...schematics.pdf |
21 August 2021, 15:45 | #54 | |
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Doing everything with discrete logic has it's price. Last edited by Mathesar; 21 August 2021 at 15:54. |
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22 August 2021, 00:32 | #55 |
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If you would make it autoconfig the memory though, there would be no speed penalty.
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22 August 2021, 06:47 | #56 |
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One potential concern here is rise time. I see the A500 schematics show a 470 ohm pull-up for AS and 2.7K on the A2000. Might be worth trying & watching with the oscilloscope I guess.
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22 August 2021, 13:54 | #57 | |
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EDIT: Catching up with comments about DTACK though, I see there's that to deal with too. For the moment I will leave it as is. Works fine as a standalone update though - nice boost in performance, lovely neat board! Last edited by GadgetUK; 22 August 2021 at 13:59. |
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17 September 2021, 17:56 | #58 |
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@Mathesar
I noticed IC U5 has a solder bridge? Is the bridge pins 8,9 and 10? Or Pins 8 and 10? It looks like the latter, but could you confirm? (Accelerator part only) Thanks |
18 September 2021, 18:32 | #59 |
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The picture is from an older revision. The revision on GitHub doesn't need a solder patch!
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19 September 2021, 16:23 | #60 |
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