Blitter fill timing

[Photon]

Yes, sometimes you post too late in the night... I guess I meant "fill blits are like copy blits but you get CPU cycles available while filling" (last paragraph). I.e. they take the same amount of active blitter cycles, the fill has idle cycles which can be utilized.

[Cyprian]

Originally Posted by Toni Wilen

Not correct, there are 4 channel combinations with fill that add extra idle cycle, including A to D copy with fill = A to D with fill takes 3 cycles, not 2.

This explains why CPU has free cycles. Normal copy will not give any cycles for CPU (if nasty bit is set)

HRM diagram is only correct if there are no other DMA activity, no fill, no linedraw. (EDIT: Only the very first rare HRM revision has extra fill information!)

Toni, I know this is stupid question, but does it emulated in WinUAE in A500 mode? and what about A1200 mode?
I'd like to do some tests in WinUAE and I'd like to be sure that my outcome will be consistent with real A500 (and A1200)

thanks

[Toni Wilen]

Originally Posted by Cyprian

Toni, I know this is stupid question, but does it emulated in WinUAE in A500 mode? and what about A1200 mode?
I'd like to do some tests in WinUAE and I'd like to be sure that my outcome will be consistent with real A500 (and A1200)

Yes but only A500 mode is accurate, A1200 isn't because CPU cycle usage is not accurate enough.

Bitplane and copper DMA is always cycle-accurate (or lots of programs would break), blitter only in cycle-exact mode.