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#21 |
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Join Date: Jul 2003
Location: Helsinki / Finland
Age: 43
Posts: 9,910
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The Minimig is a VHDL Amiga.
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#22 | |
Digital Corruption
![]() Join Date: Jan 2007
Location: Dorrigo/Australia
Age: 60
Posts: 355
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Quote:
There is a similar such project for the Atari-ST at: http://www.experiment-s.de/ which has the 68000 in the FPGA aswell. The 68k is still a bit preliminary, but it is coming along. As soon as minimig is released, I wouldn't mind trying to get it running with this 68k core. ![]() By the way, Digilent make several boards with S3-1000 variants. A Cyclone2-35 may be sufficient if you prefer Altera. If you bought their Nexys with a S3-1000, PS2 interface, VGA interface, the whole thing would cost you less than $150US. All that would be required is to build a simple Joystick/mouse interface. You could of course, add a second PS2 interface and use a PC mouse instead. Either way, it looks like a fun project. Cheers, Red |
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#23 | |
Thalion Webshrine
Join Date: Jan 2004
Location: Oxford
Posts: 14,461
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#24 | |
Thalion Webshrine
Join Date: Jan 2004
Location: Oxford
Posts: 14,461
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Quote:
I wish the author all the best though, he is the only one taking the time and effort to do anything. |
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#25 | |
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Join Date: Jul 2003
Location: Helsinki / Finland
Age: 43
Posts: 9,910
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Quote:
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#26 |
Registered User
Join Date: Sep 2005
Location: melbourne
Age: 55
Posts: 541
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Alexh, I could be wrong, but from memory Verilog supports analogue and digital circuits whereas VHDL is digital only, isn't it?
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#27 | |
Thalion Webshrine
Join Date: Jan 2004
Location: Oxford
Posts: 14,461
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Quote:
![]() Verilog and VHDL are both high level description languages and can be used to describe anything, although they are mainly used for digital and behavioural logic. Synthesisers exist for both which convert from the high level language to digital electronic gates. Verilog is a European creation but is mainly used in the USA, and VHDL was created by Americans and is mainly used in Europe. Verilog is very much like C in it's syntax. Very easy to learn and write code but due to it's flexibility it is also very easy to make accidental functional errors which are not syntactic errors. VHDL is very much type based, very intricate and explicit language. It is MUCH harder to accidentally create a functional error which is syntactically correct. Verilog is used regularly to describe netlists (low level post synthesis structures) whereas VHDL is not usually. This is mainly from the fact that the synthesis tools were written by Americans and was adopted as the industry standard. Analog is seldom (never?) designed in HDL, I think that the analog extension (Verilog-AMS) may be used in simulations, but to be honest I find the whole area "Magical". Analog is usually are done in a mixture of schematic and full custom layer design almost like a "paint" package for chips. A bit of metal here, a bit of Polysilicon there etc. Last edited by alexh; 30 January 2007 at 16:46. |
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