03 January 2013, 19:33 | #21 |
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A4000 IDE controller can work just fine under PIO-2 with the new GALS (code from yaqube iirc)
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03 January 2013, 19:51 | #22 |
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03 January 2013, 21:20 | #23 |
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04 January 2013, 18:11 | #24 | |
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Quote:
There is a timing bug which makes the speed of the GALs critical for PIO2 mode. I made a new IDEU901M.jed which helps improve the timing for PIO2 but I have not heard if Yaqube approved of it's distribution yet. SpeedGeek: Since Yaqube gave you instructions to solve the PIO2 bug he has also given you permission to test modified versions of his GAL logic. So if the new IDEU901M.jed works then just ask for permission to distribute it! Cosmos: Ok, working now on my A4000D : super !! With two Gal 10ns all is fine, but with 7ns the HD is not detected... Anyway, if ok with 10ns, it's perfect !! Last edited by SpeedGeek; 06 January 2013 at 18:31. |
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06 January 2013, 14:33 | #25 |
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Next version is available. Reworked Conner CP2024 support routine, removed extra waits for new HD's. Tell me, if any HD don't works anylonger.
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06 January 2013, 20:47 | #26 |
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New version works ok on my setup.
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21 January 2013, 17:32 | #27 |
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Next version is available, can be a few fastest.
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27 January 2013, 14:41 | #28 |
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Works nicely. But no speed obvious speed difference.
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28 January 2013, 23:05 | #29 | |
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Quote:
If you didn't see this already, Toni Wilen found the precise reason for the maxtransfer problem. Maybe it can help you verify your maxtransfer fix. Which version did you start off from? Original 3.1 or 43.something? Does this version support NSD, TD64 or both? |
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30 January 2013, 18:33 | #30 | |
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Quote:
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17 February 2013, 13:13 | #31 |
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Next version is available. Reworked IdentifyDrive and ReadCapacity routines.
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03 March 2013, 15:54 | #32 |
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Running this version for a few days now and got no problems. Keep up the good work dude!
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10 March 2013, 15:54 | #33 | |
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Next version is available. Reworked Mode Sense and Request Sense routines. Code:
;ModeSense BSR.W IdentifyDrive ; TST.L D0 ; BNE.W SetErrorStatus ; MOVEA.L $64(A3),A1 ; LEA $74(A2),A0 ; identify drive block offset ; MOVE.B 2(A1),D1 ; BMI.S lbC002524 ; minus here ; BTST #6,D1 ; bclr #6,D1 ; BEQ.S lbC002524 ; LEA -$18(SP),SP ; MOVEA.L SP,A1 ; MOVEQ #$18,D0 ; BSR.W ClearArea ; AND.B #$3F,D1 ; not necessary if bclr ; LSL.W #8,D1 ; MOVE.B #$16,D1 ; MOVE.W D1,(A1) ; MOVEQ #$18,D0 ; BRA.W lbC0025A6 ;lbC002524 AND.B #$3F,D1 ; CMP.B #3,D1 ; BNE.S lbC00257E ; LEA -$18(SP),SP ; MOVEA.L SP,A1 ; MOVEQ #$18,D0 ; BSR.W ClearArea ; MOVE.W #$316,(A1) ; MOVEQ #2,D0 ; Default number of cylinders ; BSR.W lbC0025CC ; MOVE.W D0,2(A1) ; MOVEQ #12,D0 ; BSR.W lbC0025CC ; Default number of sectors per track ; MOVE.W D0,10(A1) ; MOVE.W #$200,12(A1) ; MOVE.W #1,14(A1) ; MOVEQ #0,D0 ; BSR.W lbC0025CC ; General configuration bit-significant information ; MOVE.B D0,D1 ; LSL.B #5,D1 ; AND.B #$C0,D1 ; BTST #6,D0 ; BNE.S lbC002576 ; BSET #5,D1 ;lbC002576 MOVE.B D1,$14(A1) ; MOVEQ #$18,D0 ; BRA.S lbC0025A6 ;lbC00257E CMP.B #4,D1 ; BNE.S lbC0025C2 ; LEA -$18(SP),SP ; MOVEA.L SP,A1 ; MOVEQ #$18,D0 ; BSR.S ClearArea ; MOVE.W #$416,(A1) ; MOVE.B 2(A0),4(A1) ; MOVE.B 3(A0),3(A1) ; MOVE.B 6(A0),5(A1) ; MOVEQ #$18,D0 ;lbC0025A6 CLR.L -(SP) ; ADDQ.B #3,D0 ; MOVEA.L SP,A1 ; MOVE.B D0,(A1) ; ADDQ.B #1,D0 ; MOVE.L D0,-(SP) ; BSR.W CopyData ; MOVE.L (SP)+,D0 ; LEA 0(SP,D0.W),SP ; MOVEQ #0,D0 ; BRA.W SetErrorStatus ;lbC0025C2 ASL.W #8,D1 ; MOVE.W D1,-(SP) ; MOVEA.L SP,A1 ; MOVEQ #2,D0 ; BRA.S lbC0025A6 lbC0025CC MOVE.W 0(A0,D0.W),D0 ROL.W #8,D0 RTS ;ClearArea MOVE.L A1,-(SP) ; BRA.S lbC0025DA ;lbC0025D8 CLR.B (A1)+ ;lbC0025DA DBRA D0,lbC0025D8 ; MOVEA.L (SP)+,A1 ; RTS ; ModeSense (final version - 9 III 2013) ; input D0 (not necessary) ; output D0 (NoError) ; changed D0/D1/A0/A1 ModeSense bsr.w IdentifyDrive bne.w SetErrorStatus moveq #5,D0 ClearMS clr.l -(SP) dbf D0,ClearMS move.l $64(A3),A1 move.b 2(A1),D1 bmi.b MinusMS bclr #6,D1 bne.b MainMS MinusMS and.b #$3F,D1 cmp.b #3,D1 bne.b NoThreeMS move.w $74+2(A2),D0 ; Default number of cylinders rol.w #8,D0 move.w D0,2(SP) move.w $74+12(A2),D0 ; Default number of sectors per track rol.w #8,D0 move.w D0,10(SP) move.l #$2000001,12(SP) moveq #70,D0 ; %01000110 and.b $74(A2),D0 ; General configuration bit-significant information ror.b #3,D0 ; %11001000 bclr #3,D0 ; %11000000 bne.b NoSetMS bset #5,D0 ; %11100000 NoSetMS move.b D0,$14(SP) bra.b MainMS NoThreeMS moveq #2+3,D0 cmp.b #4,D1 bne.b CopyDataMS move.b $74+2(A2),4(SP) move.b $74+3(A2),3(SP) move.b $74+6(A2),5(SP) MainMS move.w #$0016,(SP) ; always same value moveq #$18+3,D0 CopyDataMS move.b D1,(SP) clr.l -(SP) move.l SP,A1 move.b D0,(A1) addq.b #1,D0 bsr.w CopyData lea $18+4(SP),SP bra.w NoError Code:
;RequestSense MOVE.B #1,$5D(A2) ; MOVE.L $274(A2),D0 ; LEA lbW002CA2(PC),A1 ;lbC002C52 MOVE.W (A1),D1 ; BEQ.S lbC002C5E ; AND.W D0,D1 ; BNE.S lbC002C5E ; ADDQ.W #4,A1 ; BRA.S lbC002C52 ;lbC002C5E MOVE.W 2(A1),D1 ; LEA -$12(SP),SP ; MOVEA.L SP,A1 ; MOVEQ #$12,D0 ; BSR.W ClearArea ; MOVE.B D1,2(A1) ; LSR.W #8,D1 ; MOVE.B D1,12(A1) ; MOVE.B #$70,(A1) ; MOVE.B #10,7(A1) ; LEA 3(A1),A0 ; EXG A0,A1 ; a1 is odd ; MOVE.L $68(A2),D0 ; BSR.W lbC002EB4 ; MOVE.B D0,3(A1) ; called only once ; LSR.L #8,D0 ; MOVE.W D0,1(A1) ; SWAP D0 ; MOVE.B D0,(A1) ; ADDQ.W #4,A1 ; MOVEA.L A0,A1 ; MOVEQ #$12,D0 ; BSR.W CopyData ; LEA $12(SP),SP ; MOVEQ #0,D0 ; BRA.W SetErrorStatus ;lbW002CA2 dc.w 1 ; bit 0 ; dc.w $1303 ; dc.w 2 ; bit 1 ; dc.w $604 ; dc.w 4 ; bit 2 ; dc.w $2005 ; dc.w $10 ; bit 4 ; dc.w $1203 ; dc.w $20 ; bit 5 ; dc.w $2806 ; dc.w $40 ; bit 6 ; dc.w $1103 ; dc.w $80 ; bit 7 ; dc.w $1103 ; dc.w $100 ; bit 8 ; dc.w $2105 ; dc.w $200 ; bit 9 ; dc.w $502 ; dc.w $400 ; bit 10 ; dc.w $4204 ; dc.w 0 ; other bits ; dc.w 5 ; RequestSense (final version - 9 III 2013) ; input D0 (not necessary) ; output D0 (NoError) ; changed D0/D1/A0/A1 RequestSense move.b #1,$5D(A2) moveq #-9,D0 ; ignore bit 3 and.w $274+2(A2),D0 lea ReqSenTable(PC),A0 lea 20(A0),A1 ; other bits pointer LoopRS lsr.w #1,D0 bcs.b LaterRS addq.l #2,A0 cmp.l A0,A1 bne.b LoopRS LaterRS clr.l -(SP) ; $11-14 clr.w -(SP) ; 13-12 move.b (A0)+,(SP) ; 12(A1) clr.l -(SP) ; 11-8 move.w #10,-(SP) ; 7-6, 6/7(A1) ifne MC68000 move.l $68(A2),D0 move.b D0,(SP) ; 3+3(A1) lsr.l #8,D0 move.l D0,-(SP) ; 5-2, 2(A1) else subq.l #4,SP ; 5-2 move.l $68(A2),1(SP) ; 3(A1) endc move.b (A0),(SP) ; 2(A1) move.w #$7000,-(SP) ; 1-0, (A1) move.l SP,A1 moveq #$12,D0 bsr.w CopyData lea $12(SP),SP bra.w NoError ReqSenTable dc.w $1303 ; bit 0 dc.w $604 ; bit 1 dc.w $2005 ; bit 2 dc.w $1203 ; bit 4 dc.w $2806 ; bit 5 dc.w $1103 ; bit 6 dc.w $1103 ; bit 7 dc.w $2105 ; bit 8 dc.w $502 ; bit 9 dc.w $4204 ; bit 10 dc.w 5 ; other bits |
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12 March 2013, 00:51 | #34 |
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Hiya Don,
Do you know about the SpeedyIDE BlizKick module? This module patches your scsi.device for more speed as far as I can tell. Can you build this speed-up into your scsi.device? I think the source code is available. |
17 March 2013, 14:26 | #35 |
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No, I don't know. But you can make speed tests (for this same HD and for same Amiga config) for SpeedyIDE version and optimised by me version and tell me results. I don't think that SpeedyIDE version can be fastest. I think that this is possible only if longword (move.l or move16) data transfer will be used.
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17 March 2013, 18:41 | #36 |
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It seems that SpeedyIDE used longword transfer, anyway this is not 100% good idea, due not all HD supported longword transfer, if I remember right. Anyway perhaps I make some tests.
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18 March 2013, 00:38 | #37 |
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Current version also is running fine.
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18 March 2013, 05:28 | #38 |
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23 March 2013, 14:51 | #39 | |
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Quote:
Here are speed results for some scsi device versions for: Amiga 4000 68060 75MHz 16 bit transfer (latest version) 3,001,000 32 bit transfer (v1) 2,932,000 32 bit transfer (v2) 2,932,000 It seems that 16 bit data transfer is fastest than 32 bit data transfer. Here are attached 32 bit versions, if someone want to test this. Maybe for some configs 32 bit transfer can be fastest, I suspected A600 only. Infos about speed for other Amiga configs can be useful, choose maximum value from 5 attempts. Speed infos from other scsi device like 43.4x can be useful too. |
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25 March 2013, 01:40 | #40 |
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Results for my A1200 68030 ACA1230-56Mhz (measured with SysSpeed 4.0):
16 bit transfer (latest version) 2.202 KB/s 32 bit transfer (v1) 2.545 KB/s 32 bit transfer (v2) 2.545 KB/s WELL DONE!! |
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