09 August 2024, 19:52 | #21 | |
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However, how these cycles relate to the custom chip cycles depends on the CPU speed, and thus the time may not be sufficient. |
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09 August 2024, 21:07 | #22 | |
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Another thing, I'd also do interrupt acknowledge prior to reading SERDAT, which would then act as a chipmem bus flush, so you don't have to worry about double interrupts on newer CPUs. As Thomas pointed out already. |
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10 August 2024, 01:54 | #23 | |
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From my memory a0 is set as $dff000 and a1 as pointer to data or vice versa. Then programmed interrupt code can be very short. Perhaps D0/D1/A0/A1 are scratch registers too, then not need to put on stack. But better check this because, I worked only for audio/timer interrupts. And it can works different for serial interrupts. |
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10 August 2024, 03:46 | #24 |
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Code:
_Comm_Write_Byte: lea $dff018,a0 ; set SERDATR as base A0 EOR.B D0,_comm_tx_checksum OR.W #$0100,D0 .wait_serdatr_ready: MOVE.W (a0),D1 ; SERDATR AND.W #$2000,D1 BEQ.S .wait_serdatr_ready MOVE.W D0,$30-$18(a0) ; SERDAT CMP.W #$01d5,D0 ; if a 0xD5 is sent, then immediately send a 0x5D BEQ.S .send_5d RTS .send_5d MOVE.W #$015d,D0 .wait_serdatr_ready2: MOVE.W (a0),D1 ; SERDATR AND.W #$2000, D1 BEQ.S .wait_serdatr_ready2 MOVE.W D0,$30-$18(a0) ; SERDAT RTS Then You can try this. Code:
_Comm_Write_Byte: lea $dff018,a0 ; set SERDATR as base A0 EOR.B D0,_comm_tx_checksum OR.W #$0100,D0 .wait_serdatr_ready: btst #13-8,(a0) ; SERDATR BEQ.S .wait_serdatr_ready MOVE.W D0,$30-$18(a0) ; SERDAT CMP.W #$01d5,D0 ; if a 0xD5 is sent, then immediately send a 0x5D bne.b .skipsend_5d .wait_serdatr_ready2: btst #13-8,(a0) ; SERDATR BEQ.S .wait_serdatr_ready2 MOVE.W #$015d,$30-$18(a0) ; SERDAT .skipsend_5d RTS |
10 August 2024, 11:09 | #25 |
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11 August 2024, 00:08 | #26 |
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Not only that. d0-d1/a0-a1/a5-a6 are all scratch registers. See exec/AddIntServer(). No, that the custom chip base register $dff000 is in a0 is *not* part of the specification, you need to do that yourself. In particular, because if interrupt servers are called before your code, a0 will be used *there* as scratch. See also the autodocs.
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13 August 2024, 01:59 | #27 |
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@a/b: Thank you greatly! I love the cleverness of using (a0) with post-increment to get free access to the next variable, and mighty memory-to-memory move instruction. Wow.
@Don Adan: Indeed, well played with the memory byte btst command. For some reason I wrongly assumed that chipset registers should be accessed only with 16-bit word (or optimally 32-bit for 32-bit chip ram system), but I think it is only when writing. Reading a byte is perfectly safe and fine. @Thomas: Ah well yes indeed, if one must. I feel quite sad having to put: tst.b CHIP_BASE at the end of the function to sync fast cpu with chipset. (note: is there a faster or better way to dummy-read chipset?) The reason is that on the slowest target (A500+chip ram), this wastes cycles, worsening the worst-case scenario. @a/b: I tried as an alternative to invert the interrupt ack and the serdat read, but it didn't work, at least on WinUAE. i.e.: doing: move.w #$0800, CHIP_BASE+INTREQ move.b CHIP_BASE+SERDATR+1, (a0) From what I see in the code of WinUAE, it somewhat uses an approximation in receive_next_buffered() by loading up the next serial byte in SERDATR immediately when SERDATR is being read, if the INTREQ bit 11 is low. |
13 August 2024, 11:33 | #28 | |
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Some info(s) was incompleted or buggy for me. But it was autodocs from 3.1 OS/kickstart, maybe later was fixed or I was wrong, I dont know. |
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19 August 2024, 21:56 | #29 | |
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19 August 2024, 22:06 | #30 | ||
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