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#21 |
Registered User
Join Date: Jun 2018
Location: Calgary/Canada
Posts: 247
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#22 |
Registered User
Join Date: Sep 2006
Location: Thunder Bay, Canada
Posts: 4,323
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#23 | |
Registered User
Join Date: Jun 2018
Location: Calgary/Canada
Posts: 247
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Quote:
2. Yesish 3. This is not required but helps 4. This is not required but helps You're absolutely right that running things async can have big benefits. For example, the CPU could still read from the prior burst fetch while Agnus is busy with the Copper or Blitter. Our pSRAM is more than fast enough and for chip-to-Denise, we just double/quad pump the bus. But CPU-to-chip is still a problem and the best we can do is have Gary sometimes give the CPU both odd and even cycles. This approaches but does not match AGA performance and C2P-heavy games and demos could suffer. There are potentially some ways around this though. |
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#24 |
Registered User
Join Date: Jun 2018
Location: Calgary/Canada
Posts: 247
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#25 |
Thalion Webshrine
Join Date: Jan 2004
Location: Oxford
Posts: 14,466
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Yeah, MegAChip or MiniMegi must have had a brain fart while typing.
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#26 |
C= and Amiga aficionado!
Join Date: Jul 2017
Location: Italy
Posts: 325
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Very interesting stuff!
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#27 |
Registered User
Join Date: Jun 2018
Location: Calgary/Canada
Posts: 247
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#28 |
Registered User
Join Date: Aug 2017
Location: Greece
Posts: 147
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A newly produced drop-in replacement is simply awesome!
![]() Big congratulations to Renee and the rest of the developers & contributors for all the hard work! ![]() ![]() |
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#29 |
10MARC
Join Date: Jul 2018
Location: Tucson, AZ, USA
Posts: 214
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Wow... This is a nice bit of news. I hope everything works out with it! Great job getting it to work!
If you want me (10 Minute Amiga Retro Cast) to do a review or preview of it, let me know. |
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#30 |
Zone Friend
Join Date: Aug 2002
Location: Belgium
Age: 51
Posts: 1,297
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typo in nonarkitten's github page in configuration table:
8327b (twice) ![]() |
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#31 |
Moderator
Join Date: Nov 2004
Location: Eksjö / Sweden
Posts: 5,655
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Seems an exciting prospect!
![]() It's important that blitting vs DMA saturation matches or exceeds the Blitter cycle diagram in HRM, so that the finish time of large and small blits are equal or faster. To display a correct picture, timing all the elements to the same horizontal positions as original Agnus chips is important. Copper, Blitter, or CPU changes to COLORxx, sprite pixels and positions, and bitmap pixels should match up as on original Agnus. Other aspects may be more forgiving. |
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#32 | |
Registered User
Join Date: Jun 2018
Location: Calgary/Canada
Posts: 247
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Quote:
![]() But all the firmware will be open source, so if people want to do this, then power to them. In fact, I have no problem adding stuff if people are willing to write AHI and P96 drivers and that it doesn't do anything those libraries can't already do. |
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#33 |
Registered User
Join Date: Sep 2013
Location: Poland
Posts: 868
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@Photon - well Apollo Team already have proven getting "updated" chipset is viable. It just happens some ppl (like me) don't want to abandon on-board chipset. New IC replacement with new options and 100% compatibility with old ones is pretty neat idea.
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#34 | |
Registered User
Join Date: Sep 2006
Location: Thunder Bay, Canada
Posts: 4,323
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Quote:
For this reason this is why we are trying to replace the custom components. AND making them open source so other people can help us if they can. |
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#35 | |
Registered User
Join Date: Jun 2018
Location: Calgary/Canada
Posts: 247
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Quote:
- sprite multicolour mode - sprite horizontal flip - sprite parallax mode - 8-bit chunky modes up to super hires (would need P96) - 16-bit chunky modes up to hires (ditto) - 24/32-bit chunky modes in lores (ditto) - scan doubling for everyone (without mode-promotion) - paula pan control (would need AHI drivers) - paula second channel set (ditto) - paula 16-bit audio (ditto) Sure, all are doable (some even trivially). Not until everything else is working though. |
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#36 |
Registered User
Join Date: Aug 2017
Location: Greece
Posts: 147
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#37 |
Thalion Webshrine
Join Date: Jan 2004
Location: Oxford
Posts: 14,466
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One chip that is impossible to find is the A3000 Super DMAC-04 if there was a possibility to create new Super DMACs that solve the issues lots of A3000 users have it would be a big help to a small subset of Amiga users.
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#38 |
Registered User
Join Date: Dec 2015
Location: USA
Posts: 2,961
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Not to sound like an asshole, but why do we want a replacement Super DMAC? I know because for A3000 users to support the DMA SCSI on the A3000. But with limited resources why isn't it a better idea to focus on replacing Lisa, Alice, Ramsey and Buster chips?
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#39 | |
Thalion Webshrine
Join Date: Jan 2004
Location: Oxford
Posts: 14,466
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Quote:
There are simply no sources of Super DMAC. It's obvious that you don't have an A3000, but I imagine A3000 owners, or those trying to make Chucky's ReAmiga 3000 would be glad of a source. |
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#40 | |
Registered User
Join Date: Jun 2010
Location: PL?
Posts: 2,875
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Quote:
Also there is limited demand for this particular IC. And yes, i own A3000 and i would be happy to have opportunity to get new SDMAC but let's focus on most important functionality especially with limited resources. To be honest i'm not aware is there any detailed specification for Super DMAC. SDMAC must be re-implemented based on software reverse engineering - how accurate this can be...? |
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