13 September 2019, 18:58 | #21 |
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DMACON was set because I had normal bitplane active when testing.
And I mixed $78/$7a, retested and fixed.. Also noticed that if only sprite or bitplane is active, unused cycle(s) are free. |
13 September 2019, 19:10 | #22 |
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DUAL tested. It also works.
If BEAMCON0 DUAL is set, HTOTAL becomes max horizontal length for UHRES, if it is smaller than current custom chipset mode, 7A/78/7A sequence happen every HTOTAL cycles. (=not anymore synced to normal scan lines) In this case 7A/78/7A can happen without extra cycle(s) between them because there is no refresh cycles that have higher priority. It still can steal copper cycles but not normal bitplane cycles. EDIT: Easy to test without logic analyzer, just set DUAL, HTOTAL=0 and enable UHRES. Copper loses almost all cycles EDIT2: HHPOSR appears to count all the time, even when DUAL or UHRES is disabled. Interesting programmable DMA cycle synced counter, just set DUAL without UHRES and change HTOTAL to adjust max count before wrap around. Without affecting normal display. Unfortunately range is only 0 to 255. Last edited by Toni Wilen; 13 September 2019 at 19:19. |
13 September 2019, 20:03 | #23 | |
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EDIT: Not that you can't do even on OCS with other methods, but it would be more complicated on fast processors. See for example Lionheart where the programmers have released a later version just to solve video/CPU synchronization problems (without settling down completely..). Last edited by ross; 13 September 2019 at 20:18. |
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14 September 2019, 13:26 | #24 |
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@Toni: Great find! To me from your investigation it looks like UHRES is fully implemented and works like documented so far.
Funny how long it has been sitting there without ever being used... BTW, not really UHRES related, but if you'd enable VARVBEN in BEAMCON0, and setting HTOTAL to some small value, couldn't you then get higher frequency dma audio? With a minimum value of probably $16 you'd get ~325 kHz. Display of course completely disabled, and video syncs messed up, unless you can somehow run them from the non-variable beam counter - from the description it looks a bit like CSCBEN could do that? EDIT: Interesting question also: from which beam counter do the copper and sprite (non-UHRES) comperators run? The fixed primary one or HHPOS? Last edited by chb; 14 September 2019 at 13:38. |
14 September 2019, 13:46 | #25 | ||||
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Why would Agnus internally do modulo addition if nothing sees the address? EDIT: Perhaps it comes out of Agnus address bus? It would be the most logical option. Unfortunately I don't have enough probes to check it and I really don't want to move them around.. Quote:
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Last edited by Toni Wilen; 14 September 2019 at 14:14. |
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14 September 2019, 13:49 | #26 | |
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Audio applications are the first thing that came to my mind when I read Toni's post. With the 'new' DMA counter you can feed manually AUDxDAT for a very consistent high frequency play. But you wouldn't have time to do anything else since the counter should be polled .. (well, probably some copper effects). |
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14 September 2019, 14:18 | #27 | ||||
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Did you also check address bus value or only the data bus? Quote:
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14 September 2019, 14:21 | #28 | |
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It works without glitches (as long as CPU is fast enough) because interrupt comes when first sample of AUDxDAT goes to DAC. You have 2xperiod cycles to update next AUDxDAT. |
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14 September 2019, 14:26 | #29 | |
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Data only, don't want to touch my "logic analyzer a500" too much..
But address bus makes sense (I forgot about it completely..) Quote:
EDIT: VARBEAMEN enables hsync and vsync HTOTAL/VTOTAL comparisons against normal counters (instead of using PAL/NTSC hard stops). VARVHSYEN and VARVSYEN enables output of variable hsync and vsync signals (including blanking). No idea about VARVBEN. (HARDDIS, LPENDIS, LOLDIS, VARVSYEN, VARHSYEN, VARBEAMEN, DUAL, PAL are known) EDIT2: VARVBEN is known, it simply switches Agnus strobe register generation to use variable vsync values (instead of PAL/NTSC built-in) Last edited by Toni Wilen; 14 September 2019 at 15:03. |
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14 September 2019, 14:39 | #30 | |
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14 September 2019, 14:53 | #31 | |||
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Oh, and i misread it the whole time - I assumed it is about horizontal blank, so scrap everything I wrote about VARVBEN in the posts before. |
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14 September 2019, 15:37 | #32 | |
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Suppose a normal AUDxLC and AUDxLEN but AUDxPER=62 and a standard PAL/NTSC video, then start Audio DMA. If you feed AUDxDAT exactly every 248DMA periods (62x4) with the CPU, can you effectively double the frequency? (PAL 57,2Khz in this case) Obviusly with interleaved audio data. Actually there is a 'drift' due to 227/228 DMA cycles/line vs 248 but you can 'adjust' a CPU write when needed. Post-lunch talks EDIT: Only an academic question, it is certainly not something to be implemented.. Last edited by ross; 14 September 2019 at 15:58. |
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23 September 2019, 21:31 | #33 | |
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After reading Toni discoveries i must say overall fact that UHRES is implemented mean register address can't be used by something else... bad news. Seem indirect addressing is only way to add more registers and provide backward compatibility. |
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24 September 2019, 02:37 | #34 |
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And for a non coder where all of this goes ??
Or how it could be use in a game or an application ??? What could be done with it that none coders can ear or see ?? I try to understand but without the knowledge it's impossible for a vanilla human. |
24 September 2019, 09:46 | #35 | |
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Let's see; I don't think we will see a lot of things using it. Maybe, as Ross pointed out, the additional beam counter can be used for audio playback at higher/more flexible sample rates or some demo effects that need exact synchronisation between CPU and display. The other features seem to be rather pointless without the additional hardware they were supposed to use, but there might be some creative programmer to prove me wrong. |
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24 September 2019, 09:57 | #36 | |
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That's already done. You can use up to about 56kHz (x2 of 28kHz limit) playback with using 30kHz screen modes (DblPAL/DblNTSC etc) or using this patch. |
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24 September 2019, 10:04 | #37 | ||
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About Cyber56khz, from the .readme: Requirements ------------ CyberGraphX V3 Quote:
EDIT: hmm, and you have to find a way to solve mirror zones incompatibilities (a register in the old mapping that tells you if you can use the new ones, so you can fork code) Last edited by ross; 24 September 2019 at 10:57. Reason: some additions |
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24 September 2019, 11:30 | #38 | |
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That's not the problem, at least for AGA. But not tested if it works with both patches as it should. |
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24 September 2019, 12:17 | #39 | ||
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24 September 2019, 13:18 | #40 | ||
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There is method mentioned here to ommit this.
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