08 August 2007, 20:29 | #21 |
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Excellent findings. To me this is one step closer to recreating the Amiga prototype with breadboards.
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21 May 2008, 16:39 | #22 |
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New logic analyzer findings (it has been too long..)
I finally decided to snoop RGA (custom register address bus) bus. Should have done this ages ago but I was stupid and too lazy RGA = custom address accessed, WE = write enable, INT3 = Agnus int3 pin, DMAL = Paula DMAL pin (not used yet), IPL = CPU interrupt level. Guess whats happening in these images? (hint in image names) Apparently every custom chip number is directly available in RGA bus, even if it is Agnus internal register. (RGA is used to transfer data to/from Denise and Paula, for example Agnus bitplane DMA puts BPLxDAT to RGA and does DMA from chipram) This means blitter line mode cycle diagram mystery will be finally solved in few days. EDIT: delay between bltsize and first DMA transfer looks interesting and is quite long.. Last edited by Toni Wilen; 21 May 2008 at 18:35. |
23 May 2008, 14:31 | #23 |
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toni u are a god! thk for your time, patience and devotion about "I think this explains problems with demos with vector objects because WinUAE's linedraw uses too many cycles depending on line type.. (testing soon)", you think that can be a solution for this probleme for exemple demos of virtual dream in the middle we can see that (the rest work like a charm):
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23 May 2008, 16:09 | #24 |
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Line draw mode was boring, didn't find anything interesting
It is -C-D-C-D-C-D except write is free cycle when in onedot mode and no pixel needs to be drawn. (nothing new here) 3 free cycles between write to BLTSIZE and first blit cycle are also free (this isn't exactly emulated yet) but this can't fix above demo either.. ADDED: I guess copper and blitter cycles don't align properly causing lost cycles (demo writes blitter registers using copper) Last edited by Toni Wilen; 23 May 2008 at 16:33. |
24 May 2008, 07:48 | #25 |
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oki thk for this info , like i'm a a500 maniak , please continue your work about the 500
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15 July 2008, 03:05 | #26 |
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Toni you work some mysterious magic
A logic analyzer, though...haha I admire your dedication. |
18 March 2021, 17:23 | #27 |
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Yes, necropost but on mostly on topic
Logic analyzer upgrade. After almost 14 years later.. DSLogic U3Pro32. Still to do: scope upgrade. Possibly Siglent SDS2104X Plus. (EDIT: scope upgrade done autumn 2021 + 16ch LA adapter) Main reason was much larger internal RAM (enough space for dozens of frames), much more than Logicport which barely had enough memory for single scanline. (2k samples@32 channels vs 2G divided by number of channels without RLE compression) Software is also much faster and supports programmable (in Python) decoders. Screen capture shows quickly made RGA to register names decoder. (No, I don't remember all register numbers!) Data bus uses generic "Parallel" decoder which I only modified to support 16-bits (original only supports up to 8). "AmigaRGA" is also based on "Parallel". Oddly enough software does not have built-in signal grouping support so you have to use existing decoders or write your own to get useful output. Last edited by Toni Wilen; 14 February 2022 at 09:27. Reason: name fixed |
18 March 2021, 18:36 | #28 |
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Toni breaks Google
I've been looking for a logic probe recently and so I Googled the following - no quotes etc. just what is typed below:
DSLogic U32Pro32Google comes back with no results at all. I can't ever remember seeing that! Did you mean the U3Pro32? |
18 March 2021, 18:44 | #29 |
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Fixed
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25 March 2021, 13:04 | #30 |
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I use an earlier analyser from DSLogic, and it's great. I'm using the Sigrok software with it instead though, and it allows grouping of signals. It might be worth checking out Sigrok as an alternative. (Incidentally, the DSView software is based on Sigrok sources but with some changes to the UI.)
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25 March 2021, 15:26 | #31 | |
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Quote:
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14 February 2022, 12:12 | #32 | |
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One thing about the DSLogic, they don't mention what the analogue bandwidth is. It might be able to sample at 400MHz, but what is the highest frequency signal it can reliably capture? For debugging USB some of the lower end logic analysers are too slow. I guess that's not so much of an issue for you with Amiga stuff, at least for the stuff Commodore released. My fantasy instrument would be a USB oscilloscope with 4 channels and 100MHz or more bandwidth, plus a 16 channel logic analyser. It seems like some of the Siglent scopes fit the bill, and Sigroks says that they are supported, but I can't actually find anyone who has used them and who can report on how well they actually work. |
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15 February 2022, 18:34 | #33 | ||
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Quote:
*) Photo attached. DSLogic connected to RGA and data bus (and sync signals and few others) and Siglent connected to DRAM address bus. Currently trying to solve how bitplane + refresh/strobe conflict actually "works". It would have been simpler with 48ch+ LA but.. Last edited by Toni Wilen; 15 February 2022 at 18:51. |
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15 February 2022, 20:56 | #34 | |
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What do you mean by "the blitter writes data back". The blitter write data two times? |
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15 February 2022, 21:34 | #35 | |
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Blitter line draw always does C reads but D write (you could also call it C write..) only happens when line pixel needs to be written. In onedot mode, if pixel does not need to be written, D write does not happen and bus cycle is free for other DMA channels. |
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16 February 2022, 10:10 | #36 | |
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Have you tried the Siglent with Sigrok? It is supposed to be supported and in theory could be a really powerful tool, but I suspect that in practice it's limited by the scope's memory depth. |
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21 February 2022, 17:07 | #37 | |
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22 February 2022, 14:24 | #38 | |
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If you have experience in this area it would be interesting to know how the scope's LA works, in terms of if you can capture say 10 seconds of data. There's really very little information, e.g. does it support compression. I get the impression it's mostly for correlation with an analogue signal, not deep LA use. |
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22 February 2022, 15:40 | #39 | |
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The instrument's digital channels have a max sample rate of 500MSa/s and a memory depth of 50Mpts/ch, so if you're trying to capture something that's 10 seconds long then you're only going to get 5MSa/s. That means for your 10s capture your signal is going to need to be 2.5MHz or slower. |
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22 February 2022, 15:49 | #40 | |
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