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Old 19 June 2024, 11:53   #281
Cyprian
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Originally Posted by Karlos View Post
A wild thought appears:

Consider that the limits to Akiko are in the transfer of converted planes from it's register to the chip ram.

GRIND only uses a 4 bit display depth. On an unexpanded CD32. You still have to write 8 longs to it, but you only have to transfer 4. So, it might give a significant boost to the already decent framerate on CD32.

as far as I remember GRIND uses 6bits per chunky pixel and converts it to four bitplanes. Additional bits are used for color interleaving.
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Old 19 June 2024, 13:14   #282
Karlos
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Originally Posted by Cyprian View Post
as far as I remember GRIND uses 6bits per chunky pixel and converts it to four bitplanes. Additional bits are used for color interleaving.
From a bandwidth perspective, what matters is how much data you have to move from Akiko to chip memory. If there are only 4 bitplanes, you only read Akiko 4 times and move the longs to their target planes.

The actual write and read access to Akiko itself is much faster. On the 030/70, it maxed out the bus. This is why I think an Akiko routine for a 4 plane target is a potential performance win, but at the same time, the way Dread organises it's data may make it difficult to retrofit.
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Old 19 June 2024, 17:50   #283
paraj
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Originally Posted by KK/Altair View Post
You've got the first 16 bits right (except IIRC the topmost bits are bitplane 0).
But the columns are interleaved in Dread engine, so it's not followed by B3 but A3[1] - or however you would denote the logical pixel just below A.
Thanks for the info (and the great work obviously), now it's clearer what the blits do.


This makes good use of the blitter passes to shuffle things back from the "scrambled" column layout to a more normal one for free while doing the C2P steps.


For the purposes of this thread I think it means Akiko will be close to useless. However maybe in the (very) long run the Grind team will optimize for 030+ (where blitter C2P isn't the best approach) in which case another chunky buffer layout might be on the table, and it can be revisited. But obviously A500 first
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