17 October 2022, 03:25 | #261 |
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Amigakit and AOTL maybe but, Amiga Store EU I bet would sell them, they like niche stuff.
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17 October 2022, 09:35 | #262 | |
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Digressing I know, but I'd forgotten I'd even written that review |
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18 October 2022, 03:47 | #263 |
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18 October 2022, 14:14 | #264 | |
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I remember that they had put a GAL inside the SONY floppy drive that did much of the magic. Unfortunately, I don't have the code for that GAL. http://eab.abime.net/attachment.php?...1&d=1277937563 The issue of HD floppy drive support in Paula was one of those things that commodore engineers had already thought of, but never implemented. What I never understood is why they didn't put it in the AGA. Implementing it now would be nice, if possible, as it would be easier to change the floppy drives on the Amigas. Last edited by salteadorneo; 18 October 2022 at 14:19. |
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18 October 2022, 22:31 | #265 | |||
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19 October 2022, 15:46 | #266 |
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The idea is to make it easy to change the floppy drives themselves. Using high-density floppies is a plus, not a necessity. I have two Amiga 357A and I use them regularly. Although, in real life, it is more useful to have USB ports. Great software the Posiedon. :-)
Last edited by salteadorneo; 19 October 2022 at 15:53. |
20 October 2022, 03:54 | #267 |
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I just uploaded HD Floppy Fix to the Zone. It is a collection of information that I gathered years ago about making a small pcd that adapts some pc hd floppy drives to work on an Amiga in HD mode.
It works without any software drivers. I have 2 Teac drives so equipped and they work fine. I hope that someone finds it useful. Last edited by Magic; 20 October 2022 at 04:01. |
12 November 2022, 07:57 | #268 |
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How goes the battle on this project, any headway?
Chris |
12 November 2022, 18:47 | #269 |
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Yes.
On the matter of the iCE65, Lattice refuse to grant access to developing for them. The combination of the original software AND license is impossible to get, Lattice blames Synopsys, and vice-versa, so we're giving up on that one. Which is too bad, they're cheap and plentiful. If anyone knows of an archaic (c. 2011) crack for iCEcube2, please let everyone know, but for now, the iCE65 is a dead end (1). On the matter of the iCE40, we believe we've confirmed that the HX variant is still 5V tolerant at least in as much as is needed on the Amiga, which isn't "really" a 5V device, it's TTL 5V which, by it's nature, provides strong resistors against the 5V anyway (from the pull-ups). I don't know yet if it will sustain against 5V CMOS for prolonged periods without a series resistor, but right now, all signs point to "yes." We also finally got the chips, boards and programmers all lined up. The iCE40 HX is not 100% pin compatible with the iCE65 as it adds dual PLLs with their own mini ground circuit. So we respun the boards and, being unwilling to pay more for shipping than the boards cost, get hit with a 6-ish week turn around. Sigh. So we have some boards in hand, 50-ish iCE40 chips of various sizes and we're just starting to assemble them. I'm getting the latest iCEcube2 set up and I'll import Denise first (low hanging fruit and all) to just get the basics up and running. (1) There are still two possibilities. Synopsis Synplify may still support the iCE65. It's insanely expensive though. Second is Yosys. Supporting the iCE65 might be fairly easy and supposedly, the initial versions were tested against it, and, with Lattice rather abruptly killing it, Clifford decided to move on. But we might be able to get some traction there. So that's where we're at. |
21 December 2022, 00:16 | #270 |
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Still keeping a look out for these Chips every where. Should be nice and snappy.
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27 December 2022, 15:08 | #271 |
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Questions/thoughts,
I have been probing signals around Gary lately trying to figure why E-clock phase matters in making my 14MHz accelerator work or not (spoiler: It may have to do with ROM access time of all things) and I noticed something: The _DBR/_BLIT signal going from Agnus into Gary lets Gary know whether there is a free bus slot available for the 68000. We were always told that at maximum, only half of the bus slots are available for the 68000. But is this really true? Because _DBR/_BLIT is often negated during several consecutive slots. Most noticeably during the blanking period. The reasons the 68000 doesn't get these slots is because at 7MHz the 68000 can't use any more and (probably) because of Gary's timing. So, these slots remain idle. Would it be possible with this new Gary to run the 68000 at 14MHz and allow ALL idle slots to be used by the CPU? Without any bitplane DMA the performance would be double that of 7MHz and even with bitplanes the 68000 would run faster as it could use the idle slots during the blanking period. Any thoghts? Last edited by Mathesar; 27 December 2022 at 15:31. |
27 December 2022, 17:02 | #272 | |
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Of course, if Agnus and Gary are reimplemented then the protocol between them could be changed arbitrarily. Perhaps an easy(-ish) way to experiment with that is using the Minimig core in the MiSTer project: https://github.com/MiSTer-devel/Minimig-AGA_MiSTer. |
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27 December 2022, 17:54 | #273 | |
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Maybe I can save up for a MISTer myself one day. I'd like to hack up a CPU core for MiniMig that's actually pipelined someday. |
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29 December 2022, 09:32 | #274 | |
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I have numbered the memory slots by counting the CCKQ cycles and colored the CPU access cycles in red. You can see that the CPU happily uses both the odd and even cycles. This happens because sometimes the 68000 does some internal cycles throwing it "out of sync". Now, with a 14MHz CPU Gary would not prevent us from doing back-to-back cycles. And maybe Agnus would not prevent us either. I have to do some more measurements here but I hope Agnus just multiplexes the CPU address bus onto the chipram address bus without any latches involved. I say "hope" because address setup time is the last thing that could prevent back-to-back cycles (and latches would certainly prevent that!). PS: @nonarkitten: the code for Gary that is currently in the github repo is not the latest version I think? Last edited by Mathesar; 29 December 2022 at 12:01. |
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29 December 2022, 09:43 | #275 | |
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Just another note. According to the Amiga Hardware reference manual:
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29 December 2022, 15:38 | #276 | ||
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Why would you think this? |
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29 December 2022, 15:56 | #277 | ||
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Last edited by Mathesar; 29 December 2022 at 16:08. |
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29 December 2022, 17:48 | #278 |
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Something to think about: Imagine Agnus running in a normal 7 MHz Amiga. And consider the situation when the CPU is doing an access in slot n. The CPU's AS signal will be negated some time after the access is complete, so AS will still be asserted some time after the end of slot n. The time when slot n ends is the time when slot n+1 starts. At what point should Agnus decide if the CPU actually wants to do an access in slot n+1, or just haven't negated AS yet? The resolution (I claim) is that if slot n was used by the CPU then slot n+1 may not be used by the CPU, even though slot n+1 is not assigned to any DMA channel.
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29 December 2022, 19:54 | #279 | |
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There are 2 signals to consider: BLIT - goes from Agnus to Gary to indicate there is a free slot. BLISS- goes from Gary to Agnus to indicate the CPU is going to use the free slot. See below scopetrace where you can see BLISS being asserted in sync with DTACK: When BLISS is not asserted, the CPU is not using that cycle, regardless of AS. |
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29 December 2022, 19:56 | #280 |
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Never mind, I see how it works now. You wanted to avoid latches and are using C3 in you DTACK in another way
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