Was anyone else disappointed with the A1200?

[Thomas Richter]

Originally Posted by TEG

I have another question: how the system manage to have 32 bits memory and 16 bits memory (PCMCIA) at the same time? Agnus taking care?

Not at all. It requires some separate logic on the corresponding turbo board. Agnus does not even see accesses to this memory. Thus, there is a separate memory controller and separate refresh logic on such boards.

[TEG]

Originally Posted by Thomas Richter

Not at all. It requires some separate logic on the corresponding turbo board. Agnus does not even see accesses to this memory. Thus, there is a separate memory controller and separate refresh logic on such boards.

With a board yes. But without you have 32 bits native memory and 16 bits memory from PCMCIA card.

[Thomas Richter]

Err, you seem confused. You have 24 address bits at the CPU, since it is an 68EC020. The address selection for the PCMCIA card slot is AFAIK done in Gary, which sees all address bits. The PCMCIA slot sees more than 16 address bits as it offers more than 64K address space. 16 bits is the size of the data path (data bus) from the PCMCIA slot to the system.

[robinsonb5]

Originally Posted by Thomas Richter

Err, you seem confused. You have 24 address bits at the CPU, since it is an 68EC020. .... 16 bits is the size of the data path (data bus) from the PCMCIA slot to the system.

I think the data path width was what TEG was actually asking about? I.e how the 16-bit peripherals are bridged to the 32-bit CPU data bus? (No Gary on PCMCIA-equipped machines, so it would be Gayle's domain, I think?)

[Promilus]

Ok, so I glanced over schematics and it seems PCMCIA is handled through Budgie on A1200. 16bit data bus might be kind of bummer since native data bus is 32b on A1200 - in that particular situation pcmcia fastram is slower. With A600 I think it doesn't make such difference. Keep in mind that with original attempt to solve fast ram on A1200 you'd have to dump your old expansion for a new one (so if you had just 4MB fast and wanted 8MB version with RTC you had to swap boards, if you had 68881+rtc+8mb and wanted 020@28MHz you had to swap boards...) With on-board base fastram capability you can ALWAYS keep and use that 4MB FastRAM regardless of your trapdoor upgrades as they'd essentially never conflict. So upgrading only up to 4MB fast would've been cheaper and you'd be able to keep that upgrade once you save enough money for fully 32b accelerator. That'd make 4MB fast expanded A1200 even more popular and would be easier for developers to expect on-board fast ram in most configurations (so... to actually move forward from chipram-only base machines).

[redblade]

Can confirm, My Viper MK2, 68030 @ 28mhz has the 8MB RAM in the 24bit range which means it will conflict with PCMCIA if PCMCIA was being used which is very annoying have no idea why they would have designed it like that.

[Karlos]

Originally Posted by redblade

Can confirm, My Viper MK2, 68030 @ 28mhz has the 8MB RAM in the 24bit range which means it will conflict with PCMCIA if PCMCIA was being used which is very annoying have no idea why they would have designed it like that.

Is it an EC030?

[grond]

Originally Posted by Promilus

With on-board base fastram capability you can ALWAYS keep and use that 4MB FastRAM regardless of your trapdoor upgrades as they'd essentially never conflict.

As long as reaching that on-board fastmem from the accelerator doesn't require running the fastmem bus at a lower clockspeed due to the length of the traces and the coupling through the connector. I repeat myself: put the EC020 on a small accelerator board and save the space for both CPU and FPU on the mainboard enabling physically larger accelerator boards. Offer any combination from EC020+no RAM to 030 with FPU and local fastmem right from the start. In this way you can keep the oh-so-important magical price point of 399£ and offer a better configuration with better margin.

[grond]

Originally Posted by Karlos

Is it an EC030?

The conflict is the same for my Blizzard MK3 with full 030 and 8MB of RAM.

[TEG]

Originally Posted by robinsonb5

I think the data path width was what TEG was actually asking about? I.e how the 16-bit peripherals are bridged to the 32-bit CPU data bus? (No Gary on PCMCIA-equipped machines, so it would be Gayle's domain, I think?)

Yeah I confirm, I was asking about the data bus. Thanks for your answer robinsonb5, I tend to forget there was new chips in the AGA architecture.


The definition of Gayle from Wikipidea:

Gayle replaced Gary in the A600 and A1200. It also incorporates the control logic for the PCMCIA and internal ATA interface on these systems.

In this document about Gayle specs (funny taking about the A’300 and related systems) it's mentioned:
- Address decoding and timing for Credit card connector
- Data buffer control


About Budgie, the definition of Gayle from Wikipidea::

Used in the A1200, Budgie connects the trapdoor expansion port for Zorro II-like expansions and controls additional Fast RAM.

But there's a post on EAB about it:

Budgie is a chip that serves as the main data path element in the
A1200 system. It provides the interface between the 32-bit processor
bus and the 32-bit chip memory bus, generates the RAS and CAS
select signals from the RAS and CAS timing signals that Alice
supports. It also provides a 16-bit bus buffer which can be used for
either an expansion bus or in this case the PCMCIA port data buffer.
It also includes some miscellaneous functions, notably processor clock
generation and 28Mhz/Genlock clock multiplexing.
It is implemented as a CMOS ASIC in a 128 Pin SMT package.

Advanced Amiga 1200 System 11

Internally, the data path element is similar to Bridgette or the bus
buffer/bridge logic implemented on the A3000 system. Data can be
routed to/from the 32-bit processor port to either half of the 32-bit chip
memory bus. Data can be bridged from the low order half of the chip
memory bus to the high order half to support 16-bit Amiga chip
accesses. Data read from memory is latched to meet the processor
data hold requirements. CAS select logic is used to prevent contention
when bridging the two halves of the chip bus.

The spare 16-bit expansion port (used for PCMCIA duty in the A1200)
provides a simple path to/from the 16-bit processor port. The direction
is dependent on the X-NOR of R_W and _BGACK signals to support
either expansion bus or several purpose buffer requirements.

The memory decoding takes the RAS and CAS timing signals
provided by Alice and the multiplexed address bus and generates
appropriate selection for 32-bit accesses. It also uses A1/A0 and
SIZ1/SIZ0 on processor accesses to do the right decoding there.

It supports 2-banks of 32 bit memory with 9-bit addressing for a total of
2M-bytes of chip memory. RAS selection is used for bank selection,
CAS selection is used for byte write control and to avoid contention on
bridged reads. Refrcsh is done with CAS before RAS and the logic
must assert all RAS and CAS signals during refresh cycles.

The processor clock generation simply X-NORS the 7MHz and *CDAC
clocks to generate a 14MHz processor clock. The 28MHz/Genlock
clock multiplexor is a simple 2 input multiplexor. It has no connection
with the rest of the logic and can be used for other functions if desired.
The CCK/4 output is provided for the PAL color burst generation
circuitry.

So it talk about "the 16-bit processor port", I guess it refer to the addresses port. For the data I guess it buffer the 16 bits x2 and present 32 bits to the 68020?

Thx Promilus for your search.

[grond]

Originally Posted by TEG

So it talk about "the 16-bit processor port", I guess it refer to the addresses port. For the data I guess it buffer the 16 bits x2 and present 32 bits to the 68020?

I doubt this. I would assume that the 16bit processor port refers to the lower 16bits of the data bus and the signals that signal a word access. And I also doubt that any data gets buffered for 32 bit reads. That would be useful after all but require a few dozens of flip-flops when you can simply make the CPU read words. It's Commodore, remember?

[TEG]

Originally Posted by grond

I doubt this. I would assume that the 16bit processor port refers to the lower 16bits of the data bus and the signals that signal a word access. And I also doubt that any data gets buffered for 32 bit reads. That would be useful after all but require a few dozens of flip-flops when you can simply make the CPU read words. It's Commodore, remember?

OK, I did not thought about the trick to simply put the upper 16 bits data bus to 0. I will finally manage to grasp a bit how all this work...

I wonder when the A600 dev started because I guess, seeing the PCMCIA port management is dispatched on two chips, it took some time to make it work and it was more or useless at the time.

[No.3]

Originally Posted by grond

As long as reaching that on-board fastmem from the accelerator doesn't require running the fastmem bus at a lower clockspeed due to the length of the traces and the coupling through the connector. I repeat myself: put the EC020 on a small accelerator board and save the space for both CPU and FPU on the mainboard enabling physically larger accelerator boards. Offer any combination from EC020+no RAM to 030 with FPU and local fastmem right from the start. In this way you can keep the oh-so-important magical price point of 399£ and offer a better configuration with better margin.

I can only quote myself:

Originally Posted by No.3

Yes, I know, a lot of people will start with "costs too much" - but hey, look onto the A1200 mainboard, Commodore did so much crap with this, so the "costs too much" 'argument' is not valid.

I wonder following: Why did Commodore not place the CPU on a small card for the trapdoor expansion slot?

* Then they could have easily offered a very low cost A1200 with only 2 MB Chip and no HD and a low cost A1200 2 MB Chip with a 40 MB HD and 020 @ 14 MHz.
* As well they could have easily offered a high end A1200 with additional 1 MB Fast and with/out 40-80 MB HD and 020 @ 14 MHz but due to the Fast Ram the 14 MHz 020 would have been almost twice as fast as in the low cost A1200.
* One or two years later, with dropping CPU, memory and HD prices they could have offered a very high end A1200 with 2 MB Fast an 120+ MB HD and 020 @ 25 MHz making this version almost twice as fast as the previous high end version ?!?!??!????

[TEG]

@No.3

That mean the trapdoor expansion slot would have not been available for something else than cpu/memory extensions. I wonder, no others kind of extensions was done for the 1200?

[Promilus]

No, not really. Mediator uses trapdoor connector but is passthrough afaik, other than that it was only rtc, mem, cpu (&fpu) and sometimes scsi as a cherry on top.

[No.3]

Exactly! And, where is the difference using the trapdoor for other extensions if there is a original Commodore 1220 card plugged in or a Blizzard or ACA 12x0 card ?!? And most likely, the few other trap door extension I know, you won't like to use these with a 020 2MB Chip A1200. ;-)

[redblade]

Originally Posted by Karlos

Is it an EC030?

It was a full 68030 with MMU, and MAX 8MB RAM expansion, The other Viper expansion allowed for more than 8MB

Why would it matter if it was a EC030? The EC030 has full 32-BIT memory range?

[Thomas Richter]

The 68EC030 has a full 32 bit address range, but no (functional/tested) MMU. However, the CPU itself is not so important - the question is where a particular expansion maps its RAM. For the 68EC020, the only chance is in the 24-bit address space, yes. But even if the CPU has a full 32 bit address space - if the board places its RAM overlapping with the PCMCIA address space, it will either create the above conflict, or the board needs to bypass PCMCIA access completely.

[No.3]

If the turbo cards memory conflicts with the PCMICA depends on the address space where the memory is mapped to. "Smart" turbo cards map the memory into the Zorro III address space, which requires a CPU with a full 32 bit address space i.e. a full (no EC) 68020 or any 68030 or higher.

[abu_the_monkey]

That mean the trapdoor expansion slot would have not been available for something else than cpu/memory extensions.

if had been designed like that from the start it wouldn't matter.

It would have evolved just the same but opened up more opportunities for commodore and the end user.

afaik there were only accelerator cards for the trapdoor/cpu slot other than the planned (and never released) cd1200.

The various bus board solutions had pass throughs iirc.