DSKINDEX bit

[mark_k]

Something I noticed when testing (using WinUAE but I assume this matches a real Amiga).

Reading the Amiga Hardware Reference Manual, the CIA B ICR register ($BFDD00) FLAG bit (bit 4) is shown as DSKINDEX* which implies that signal is active low. And it does seem to be; reading $BFDD00 while running a program which uses trackdisk.device to read a disk returns $10 most of the time, occasionally $00. But when no drive is selected (no disk activity) that bit always reads as zero.

Edit: I think that's wrong. It seems the FLAG bit doesn't track the state of the index line directly, but is set when the CIA chip "sees" an index pulse. It is reset on reading CIA B ICR. So basically, CIABICR FLAG bit = 1 means "there has been an index pulse since the register was last read". (I don't know whether the FLAG bit goes high on the leading or trailing edge of the index pulse, or what delay there is between the actual floppy drive index line transition and the FLAG bit being set in CIABICR.)

[mark_k]

Another disk index-related question, I might as well write here instead of making a new thread.

Suppose I'm polling in a tight loop for the disk index pulse. Which has lower latency: reading CIA B ICR or checking the EXTER bit in INTREQR?

CIA registers are slower to read than custom chip registers. But is there a delay between the CIA B ICR FLAG bit being set and the EXTER bit in INTREQR being set? Assume interrupts and display/blitter/sprite DMA are disabled and code is running from fast RAM.

Loop reading the CIA B ICR FLAG bit directly. D0 contains CIAICRB_FLAG (4), A0 points to CIAB ICR B ($BFDD00).

 TST.B	(A0)		;Make sure bit is clear before looping 
WaitForIndex:
 BTST.B	D0,(A0)
 BEQ.B	WaitForIndex

Loop checking the EXTER bit in INTREQR. D1 contains INTB_EXTER-8, A1 points to INTREQR.

 TST.B	(A0)		;Clear FLAG bit in CIA B ICR
 MOVE.W	#INTF_EXTER,(intreq).L	;Clear EXTER bit

WaitForIndex2:
 BTST.B	D1,(A1)
 BEQ.B	WaitForIndex2

[IFW]

CIAs are driven by the E clock (much slower, see the hardware manuals for 68K family), and clocking in external signals is possibly not a single cycle operation either. So chances are, you want to read INTREQ.

[Toni Wilen]

EXTER signal comes from CIA and CIA interrupt generation is also synced to E-clock and there is also 2 color clock delay before Paula sees changed interrupt state.

Also I think it is also possible to read active interrupt status from CIA register before CIA enables the physical interrupt signal. (I did test this long time ago.)

So technically reading CIA register should be (slightly) faster.

EDIT: but if you only have chip ram (or slow ram) and CPU without instruction cache, it probably makes no difference because even in fastest case your checking loop has at least 2 instruction fetches (2x4 CPU clocks in best case), which will add at least 1 extra E-clock of noise to your calculations.

[IFW]

I should have checked the schematics