what's the logic in H instruction ?

[jotd]

WinUAE 5.0.0, "more compatible" off to avoid prefetch

-1 225/312 0009ea60 5000                     addq.b #$08,d0
-1 225/312 0009ea62 b02b 0002                cmp.b (a3,$0002) == $00096daf [97],d0
-1 226/312 0009ea66 65f0                     bcs.b #$f0 == $0009ea58 (F)
-1 226/312 0009ea68 0400 000f                sub.b #$0f,d0
-1 000/000 0009ea6a 000f                     illegal
-1 003/298 0009dfd8 16c0                     move.b d0,(a3)+ [00]
-1 000/105 0009e356 1001                     move.b d1,d0
-1 000/300 0009dfc4 48e7 4030                movem.l d1/a2-a3,-(a7)
-1 000/210 0009d11e 13c0 0009 6aa4           move.b d0,$00096aa4 [20]

First part is OK, then there's this "illegal" which is probably wrong decode (in the middle of SUB), then the PC values are completely different from line to line... it can't be interrupts! 0009dfd8 then 0009e356 then 0009dfc4 then 0009d11e what???

I wonder if this feature isn't broken. It used to work pretty well, and since a few months I never got it working properly again.

[Toni Wilen]

Exact CPU config needed. (Does not happen here if 68000 without more compatible)

[Rock'n Roll]

The H-command delivers more output if more is enabled !

1. cycle exact is disabled, without dma-debugger
2. cycle exact is disabled, dma-debugger is enabled
3. cycle exact is enabled, dma-debugger is enabled

1. cycle exact is disabled, without dma-debugger (this History output is quite ideal!)

 0 082/080 0002a6f6 33fc 0000 00df f042      move.w #$0000,$00dff042			; Cycles: 10 Chip, 20 CPU. (V=80 H=72 -> V=80 H=82)
 0 092/080 0002a6fe 23fc 0001 0508 00df f054 move.l #$00010508,$00dff054		; Cycles: 10 Chip, 20 CPU. (V=80 H=82 -> V=80 H=92)	
 0 106/080 0002a708 33fc 0000 00df f066      move.w #$0000,$00dff066			; Cycles: 14 Chip, 28 CPU. (V=80 H=92 -> V=80 H=106)
 0 116/080 0002a710 33fc 0050 00df f058      move.w #$0050,$00dff058			; Cycles: 10 Chip, 20 CPU. (V=80 H=106 -> V=80 H=116)

Disassembly/ History
>d            0002a708 33fc 0000 00df f066      move.w #$0000,$00dff066
>H  0 106/080 0002a708 33fc 0000 00df f066      move.w #$0000,$00dff066

first field in a History output:
-1 00fc0f94 60e6 bra.b #$e6 == $00fc0f7c (T)
0 0002a5a4 0c80 0000 5000 cmp.l #$00005000,d0

It is CPU interrupt mask. (-1 = mask=0, supervisor mode. 0 = mask=0, user mode) (SR=0014 T=00 S=0 M=0 X=1 N=0 Z=1 V=0 C=0 IM=0 STP=0)

2. cycle exact is disabled, dma-debugger is enabled - this output shows also the CHIP-DMA cycles

0 204/080 0002a6fe 23fc 0001 0508 00df f054 move.l #$00010508,$00dff054
 - 00 CD BPL2   112         0000    0001A8D6
 - 00 CF BPL1   110         0000    000158D6
 - 00 D0              1
 - 00 D1 BPL2   112         0000    0001A8D8
 - 00 D3 BPL1   110         0000    000158D8
 - 00 D5 BPL2   112         0000    0001A8DA
 - 00 D7 BPL1   110         0000    000158DA
 - 00 D9 BPL2   112         0000    0001A8DC
 0 218/080 0002a708 33fc 0000 00df f066      move.w #$0000,$00dff066
 - 00 DB BPL1   110         0000    000158DC
 - 00 DD BPL2   112         0000    0001A8DE
 - 00 DF BPL1   110         0000    000158DE
 0 001/081 0002a710 33fc 0050 00df f058      move.w #$0050,$00dff058

3. cycle exact is enabled, dma-debugger is enabled - this is the completest output with all cycles: CPU and Chip cycles

0 219/080 0002a6fe 23fc 0001 0508 00df f054 move.l #$00010508,$00dff054
 - 00 DB BPL1   110         0000    000158DC
 - 00 DC CPU-RWI            0508    0002A702
 - 00 DD BPL2   112         0000    0001A8DE
 - 00 DE CPU-RWI            00DF    0002A704
 - 00 DF BPL1   110         0000    000158DE
 - 00 E0 CPU-RWI            F054    0002A706
 - 00 E2 CPU-RWI            33FC    0002A708
 - 00 01 CPU-WWD            0001    00DFF054
 - 00 03 RFS0   03C           *=    0002CA00
 - 00 04 CPU-WWD            0508    00DFF056
 - 00 05 RFS1   1FE           *F    0002CA02
 - 00 06 CPU-RWI            0000    0002A70A
 0 007/081 0002a708 33fc 0000 00df f066      move.w #$0000,$00dff066
 - 00 07 RFS2   1FE                 0002CA04
 - 00 08 CPU-RWI            00DF    0002A70C
 - 00 09 RFS3   1FE                 0002CA06
 - 00 0A CPU-RWI            F066    0002A70E
 - 00 0C CPU-RWI            33FC    0002A710
 - 00 0E CPU-WWD            0000    00DFF066
 - 00 10 CPU-RWI            0050    0002A712
 0 017/081 0002a710 33fc 0050 00df f058      move.w #$0050,$00dff058

One suggestion would be, to write the addresses among each other, thats means a little reordering the CPU and Chip Cycles.
In the first field there is always a '00'? What is the purpose?

0 195/080 0002a6ec 66f6                     bne.b #$f6 == $0002a6e4 (F)
 - 00 C3 BPL1   110         0000    000158D0
 - 00 C5 BPL2   112         0000    0001A8D2
 - 00 C6 CPU-RWI            0100    0002A6F0
 0 199/080 0002a6ee 33fc 0100 00df f040      move.w #$0100,$00dff040


 IM/ hpos/line /address / DMA channel / DMA channel nr. / value
 0 195/080 0002a6ec 66f6                     bne.b #$f6 == $0002a6e4 (F)
 -   C3    000158D0  BPL1   110         0000
 -   C5    0001A8D2  BPL2   112         0000
 -   C6    0002A6F0  CPU-RWI            0100
 0 199/080 0002a6ee 33fc 0100 00df f040      move.w #$0100,$00dff040

also it mixed a little bit decimal and hex numbers, but it is no problem: for the dma debugger:
>v !80 !195
Line: 50 80 HPOS C3 195: