Clearing bits in ciaicr mask

DJ Mike · Yesterday, 08:45

Does clearing bits in a ciaicr mask - e.g. move.b #CIAICRF_TB,(_ciaa+ciaicr) - immediately mask them if they are already set (i.e. when the register is next read)? I want to reset a bit in the icr without affecting other bits that may already be set. I can't just read ciaicr to clear it because that clears the entire register.

Perhaps it is a moot point, since if an interrupt is signalled to ciaicr and I have a ports interrupt installed, then I would expect the interrupt to occur before my code is setting ciaicr elsewhere. So it might be a redundant question.

ross · Yesterday, 09:23

icr contains two registers at the same address, one read-only and one write-only.
They are completely separate.

So even if you write a specifica mask, when you read the register it will contain the 'historical situation' of the interrupt requests, even those that were instantly masked.
This means that if you have pending interrupts, they remain pending after writing.

DJ Mike · Yesterday, 09:43

Thanks for clarifying ross. That's helpful to me to be aware of. Thankfully I don't think it materially impacts what my program is doing.

Photon · Yesterday, 14:35

Yesterday, 08:45	#1
DJ Mike Registered User Join Date: Nov 2005 Location: United Kingdom Age: 41 Posts: 111	Clearing bits in ciaicr mask Does clearing bits in a ciaicr mask - e.g. move.b #CIAICRF_TB,(_ciaa+ciaicr) - immediately mask them if they are already set (i.e. when the register is next read)? I want to reset a bit in the icr without affecting other bits that may already be set. I can't just read ciaicr to clear it because that clears the entire register. Perhaps it is a moot point, since if an interrupt is signalled to ciaicr and I have a ports interrupt installed, then I would expect the interrupt to occur before my code is setting ciaicr elsewhere. So it might be a redundant question. Last edited by DJ Mike; Yesterday at 09:00.

Yesterday, 14:35	#4
Photon Moderator Join Date: Nov 2004 Location: Eksjö / Sweden Posts: 5,738	More on the ICR in this overview.

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Yesterday, 09:23	#2
ross Defendit numerus Join Date: Mar 2017 Location: Crossing the Rubicon Age: 54 Posts: 4,508	icr contains two registers at the same address, one read-only and one write-only. They are completely separate. So even if you write a specifica mask, when you read the register it will contain the 'historical situation' of the interrupt requests, even those that were instantly masked. This means that if you have pending interrupts, they remain pending after writing.

Yesterday, 09:43	#3
DJ Mike Registered User Join Date: Nov 2005 Location: United Kingdom Age: 41 Posts: 111	Thanks for clarifying ross. That's helpful to me to be aware of. Thankfully I don't think it materially impacts what my program is doing.

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