A500+ mystery issue - help please!

[stevew]

Hi,

I have an A500+ board that is behaving strangely, when I boot it using diagrom it fails all memory tests, when diagrom starts to write different values to addresses every one fails. It will always read the same values for a given address no matter what it is trying to write. The upper 16bits are different to lower 16 bits.

Using the scope a noticed CAS_U and CAS_L and WE were at about 4v and struggling to be pulled down to ground to produce a square wave, there is a very small square wave (vpp 700mv). I traced these signals back to Angus. Looking at the Agnus block diagram I noticed A19 looks likes its an input into CAS generation, A19 has the same flattened square wave signal along with A17,A18,A20, and A23. A1-16 have normal 4.7v vpp square waves.

The agnus socket is new, I replaced U10, U12, and U13, not U11 and replaced U34, U35 and U32, the Gary socket is also new.

All custom chips and the CPU are known good and work in other boards.

Not sure what else to try apart from replacing every DRAM, but not sure this is the issue here.

Does anyone have any ideas on what I can try next?

Thanks

[Elmo Putney]

Could you post a picture of the dodgy square wave?

[stevew]

Yes sure, here is an image of the CAS signal

[Elmo Putney]

It looks like it's being pulled up to vcc, what is the resistance between cas and vcc? I have an A600 on the bench and it shows >2MOhms to vcc (and gnd).

[levo-ace]

Are any of the ram or logic chips getting hot . Pulling signals up to that level will generate some heat .

[Elmo Putney]

Next question was going to be - have you got access to a thermal imaging camera

[stevew]

Originally Posted by levo-ace

Are any of the ram or logic chips getting hot . Pulling signals up to that level will generate some heat .

No, all normal to touch. There are not many left in the address data circuit ?? The only is RAM which I have not touched and U11.

I am not sure how 1 faulty DRAM will cause the CAS signal to look like it does, also the WE signal looks the same. My logic is U11 is faulty then the (lower half of RAM would be effected, DRD0-7) and show up in Diagrom output

[stevew]

Originally Posted by Elmo Putney

It looks like it's being pulled up to vcc, what is the resistance between cas and vcc? I have an A600 on the bench and it shows >2MOhms to vcc (and gnd).

Just tested and OL for CASU and CASL to VCC, from CASU and CASL lower to GND is also Open Circuit (OL)

[stevew]

Originally Posted by Elmo Putney

Next question was going to be - have you got access to a thermal imaging camera

no I'm afraid I don't have one of those

[stevew]

I also checked LDS and UDS signals as I believe these are used by Agnus to generate CASL and CASU, the signal on these looks okay. AS and ROMEN I think are okay. Wondering if Gary generates these signals....

[Elmo Putney]

https://gamesx.com/wiki/lib/exe/fetc...ice_manual.pdf

https://archive.org/details/A500_Tra...e/n51/mode/2up

A couple of links I stumbled on at the weekend - may be of use to you.

[stevew]

Originally Posted by Elmo Putney

https://gamesx.com/wiki/lib/exe/fetc...ice_manual.pdf

https://archive.org/details/A500_Tra...e/n51/mode/2up

A couple of links I stumbled on at the weekend - may be of use to you.

Thanks, I've got the service manual, the other link is interesting, seems to point to Agnus. Maybe I should take the new Agnus socket off and check......