05 August 2023, 05:23 | #41 |
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05 August 2023, 07:10 | #42 |
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05 August 2023, 16:11 | #43 |
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05 August 2023, 18:23 | #44 |
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Sounds interesting! 70Hz 030!
Is this extreme overclocking achieved via a custom cooling solution? |
05 August 2023, 19:26 | #45 |
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Yes, that's awesome! You should definitely create a new thread and provide some more details so you can get the appropriate praise!
(And bustest results from my P5 Blizzard 1260 to stay on topic): Code:
BusSpeedTest 0.19 (mlelstv) Buffer: 262144 Bytes, Alignment: 32768 ======================================================================== memtype addr op cycle calib bandwidth fast $681B8000 readw 67.1 ns normal 29.8 * 10^6 byte/s fast $681B8000 readl 113.3 ns normal 35.3 * 10^6 byte/s fast $681B8000 readm 110.3 ns normal 36.3 * 10^6 byte/s fast $681B8000 writew 82.4 ns normal 24.3 * 10^6 byte/s fast $681B8000 writel 164.7 ns normal 24.3 * 10^6 byte/s fast $681B8000 writem 165.0 ns normal 24.2 * 10^6 byte/s chip $00018000 readw 894.7 ns normal 2.2 * 10^6 byte/s chip $00018000 readl 895.1 ns normal 4.5 * 10^6 byte/s chip $00018000 readm 894.9 ns normal 4.5 * 10^6 byte/s chip $00018000 writew 730.4 ns normal 2.7 * 10^6 byte/s chip $00018000 writel 728.8 ns normal 5.5 * 10^6 byte/s chip $00018000 writem 729.3 ns normal 5.5 * 10^6 byte/s |
05 August 2023, 19:29 | #46 |
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05 August 2023, 19:57 | #47 |
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04 June 2024, 01:39 | #48 |
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This is the N2630 50MHz 68030 board project by jasonbeer of Github. Board purchased off Amibay, one of a series built by steveed. v4.0.1a, 128MB+8MB, and I added a Sandisk Ultra 4MB to it. (FWIW - I clocked it with Ultra settings at 9481K on RSCP_020 v1.15)
Fresh OS 3.2.2.1 install over the v3.2.2 v47.111 ROM. A full MuLibs 68030.library install, but I only added FastROM as all the memory is AutoConfig. System is fully booted to Workbench. NTSC machine but a PAL 2MB MegAChip, non-interlaced standard Workbench. One notable tweak: Just prior to SetPatch, I forced the Z2 memory to priority to 21 (vs default of 0), with a memory priority tweaking tool from AmiNet. This pushed the Z2 range FastRAM ahead of the Z3 FastRAM for first-allocation requests. This was because I noticed the Z2 RAM was a hair faster at times in my tests with BusTest. BusSpeedTest 0.19 (mlelstv) Buffer: 262144 Bytes, Alignment: 32768 ======================================================================== memtype addr op cycle calib bandwidth chip $00018000 readw 1024.7 ns normal 2.0 * 10^6 byte/s chip $00018000 readl 1606.9 ns normal 2.5 * 10^6 byte/s chip $00018000 readm 1200.6 ns normal 3.3 * 10^6 byte/s chip $00018000 writew 575.1 ns normal 3.5 * 10^6 byte/s chip $00018000 writel 1150.7 ns normal 3.5 * 10^6 byte/s chip $00018000 writem 1149.5 ns normal 3.5 * 10^6 byte/s fast $002C0000 readw 144.8 ns normal 13.8 * 10^6 byte/s fast $002C0000 readl 207.7 ns normal 19.3 * 10^6 byte/s fast $002C0000 readm 195.6 ns normal 20.4 * 10^6 byte/s fast $002C0000 writew 104.8 ns normal 19.1 * 10^6 byte/s fast $002C0000 writel 107.6 ns normal 37.2 * 10^6 byte/s fast $002C0000 writem 96.1 ns normal 41.6 * 10^6 byte/s user $04100000 readw 145.7 ns normal 13.7 * 10^6 byte/s user $04100000 readl 208.7 ns normal 19.2 * 10^6 byte/s user $04100000 readm 197.2 ns normal 20.3 * 10^6 byte/s user $04100000 writew 105.0 ns normal 19.0 * 10^6 byte/s user $04100000 writel 107.3 ns normal 37.3 * 10^6 byte/s user $04100000 writem 97.9 ns normal 40.9 * 10^6 byte/s The user memory is the Z3 128MB above. The Z3 speed is slightly slower, and the gap slightly wider, if I don't do the memory priority tweak. The user memory is the Z2 8MB in the detail below: user $00300000 readw 145.4 ns normal 13.8 * 10^6 byte/s user $00300000 readl 207.8 ns normal 19.3 * 10^6 byte/s user $00300000 readm 196.6 ns normal 20.4 * 10^6 byte/s user $00300000 writew 104.4 ns normal 19.2 * 10^6 byte/s user $00300000 writel 107.6 ns normal 37.2 * 10^6 byte/s user $00300000 writem 96.8 ns normal 41.3 * 10^6 byte/s fast $40178000 readw 154.5 ns normal 12.9 * 10^6 byte/s fast $40178000 readl 227.5 ns normal 17.6 * 10^6 byte/s fast $40178000 readm 214.6 ns normal 18.6 * 10^6 byte/s fast $40178000 writew 145.3 ns normal 13.8 * 10^6 byte/s fast $40178000 writel 146.8 ns normal 27.3 * 10^6 byte/s fast $40178000 writem 132.0 ns normal 30.3 * 10^6 byte/s I have a query in to the designer if this speed quirk I found is expected. One way or another, in my opinion, it's still a good performing 68030 card. Quirk located. MuLibs does not enable Data Burst by default. One must add the CPU >nil: databurst somewhere during startup (after SetPatch) to enable it. System: 68030 68882 68030-MMU FastROM (INST: Cache Burst) (DATA: Cache Burst) Updated Read Z3 memory speeds with the memory tweak I mentioned not used: BusSpeedTest 0.19 (mlelstv) Buffer: 262144 Bytes, Alignment: 32768 ======================================================================== memtype addr op cycle calib bandwidth fast $401A8000 readw 111.0 ns normal 18.0 * 10^6 byte/s fast $401A8000 readl 141.1 ns normal 28.3 * 10^6 byte/s fast $401A8000 readm 171.6 ns normal 23.3 * 10^6 byte/s No change in write speeds with Data Burst enabled. Last edited by thebajaguy; 13 June 2024 at 04:48. |
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