Was anyone else disappointed with the A1200?

[Amigajay]

Are we getting A.I’d ?!

[TEG]

Originally Posted by hammer

The problem is Commodore West Germany's A2000 (1987) didn't have a stable high-resolution mode for business use cases and the A2000 wasn't mass-produced like the A500. By defeating Amiga Ranger in 1987, it killed Amiga's stable high resolution for business use cases near Windows 2.0's Dec 1987 introduction. For the larger DTP and GUI professional office markets, A2000 was hobbled from the beginning.

I think it really was the turning point. The battle to have a part of the professional market cake was definitely lost after this move of discarding Ranger (1024×1024 pixels with 128 colours).

VGA is 1987, the year of the A2000 yeah, so the advance of the Amiga was lost at this point. The real 256 colours mode was the definitive "killer PC application".

Not to mention that Apple owned the laser printers market (they built it, the LaserWriter is 1985).

[Gorf]

Originally Posted by TEG

I think it really was the turning point. The battle to have a part of the professional market cake was definitely lost after this move of discarding Ranger (1024×1024 pixels with 128 colours).

I am still convinced the "Ranger_Chipset" is just ECS with its UHRES register and some additional VRAM for one more plane in addition to the 6 OCS/ECS planes.

The rumors made 128 colors out of this 7 planes but it is actually your 6 low resolution planes with max 64 colors in EHB plus one independent b/w HiRES plane with its own DAC.
(still a very good Idea for A2000 A3000 type of computers in the late 80s)

Later on this method could have been expanded to support chunky pixels and colour (with an additional CLUT for 8bit - no CLUT needed for 16bit) ... that's when we end up with the same functionality at my "Bypass" would provide.

[Gorf]

Originally Posted by hammer

With a bypass display model, an Amiga game or application with chunky pixel usage would trigger the switch over to the new display adapter.

Not necessarily a new adapter, but just a fast-path to the existing DAC/Vidiot would be sufficient...

32 bit x 50 Mhz memory bus is 200 MB/s which rivals 3DO's.

There was no fast enough DRAM in 92/93 to saturate such a bus:

Fast DRAM of that time was rated "70ns" or "60ns", which leads to a total roundtrip time of 120-140 ns, which is equivalent to a frequency of 7-8 MHz

Yes: DRAM really was THAT slow.
Even with static page oder static column tricks and interleaving banks of DRAM chips the best transfer rates for long bursts would be around 50 MB/s (and much less for single random accesses)

[TEG]

Originally Posted by Gorf

I am still convinced the "Ranger_Chipset" is just ECS with its UHRES register and some additional VRAM for one more plane in addition to the 6 OCS/ECS planes.

The rumors made 128 colors out of this 7 planes but it is actually your 6 low resolution planes with max 64 colors in EHB plus one independent b/w HiRES plane with its own DAC.
(still a very good Idea for A2000 A3000 type of computers).

Precisely, the absence of VRAM in ECS change all no? I'm really not sharp enough about VRAM and bandwidth numbers but the question is, would it be possible to go as up to 8 planes (256 colours) at 320x200 like the VGA mode 13h ?

Of course the other question would be to know that the competition will release that in 1987 but it's another debate.

I would really love to join someone of the original team who can definitively shed light on what was planned for Ranger.

[Gorf]

Originally Posted by TEG

Precisely, the absence of VRAM in ECS change all no? I'm really not sharp enough about VRAM and bandwidth numbers but the question is, would it be possible to go as up to 8 planes (256 colours) at 320x200 like the VGA mode 13h ?

Yes sure, this would be possible, but you need an additional CLUT and you need a way to write your colour information to the CLUT registers ... or you decide to use a fixed 256-colour-palette.

since the OCS/ECS already gives you quite good colour at low resolutions, I would assume Ranger was meant to add a monochrome 1024 pixel-wide mode, that one would most likely display on a second monitor.

So you would have e.g. your cheap TV-set hooked up for games and your monochrome monitor for high-res productivity applications.

And like on the C128 you would be able to have both displays running simultaneously and have e.g. a raytracer with your wireframe representation on the monochrome display and the rendering on the colour TV.

[hammer]

Originally Posted by TEG

I think it really was the turning point. The battle to have a part of the professional market cake was definitely lost after this move of discarding Ranger (1024×1024 pixels with 128 colours).

VGA is 1987, the year of the A2000 yeah, so the advance of the Amiga was lost at this point. The real 256 colours mode was the definitive "killer PC application".

Not to mention that Apple owned the laser printers market (they built it, the LaserWriter is 1985).

It doesn't need to be VRAM enabled solution. ECS with 640x480p 4 colors is between monochrome Mac and 16 color Mac II model/PC VGA 640x480p 16 colors competition.

1987 Mac II models:
256 KB VRAM, 640×480p 16 color and 512×384p 256 colors.
512 KB VRAM, 640×480p 256-color.

A2000 with ECS in 1987 would be okay for WYSIWYG word processors and DTP, but it's not the leader.

32-bit Chip RAM via DRAM chips Denise+ (2X) without Lisa's "double pump"(4X) would have supported 4 bitplanes 640x480p, 32-bit wide sprites, 4096 color palette and 320x200/256p 8 bitplanes (256 colors). Agnus would need to be modified for 8 bitplanes aware. It avoids the difficulty of Lisa's 24-bit palette AAA backport.

Lisa's 32-bit "double pump" (28MB/s) supports 640 × 480p 256 colors which is entry-level SVGA and the 24-bit color palette is above the mandatory SVGA's 18-bit palette.

It doesn't need to be an extreme upgrade with VRAM.

[Gorf]

Originally Posted by hammer

32-bit Chip RAM via DRAM chips Denise+ (2X) without Lisa's "double pump"(4X) would have supported 4 bitplanes 640x480p, 32-bit wide sprites, 4096 color palette ...

It would ave been also straight forward to go from 4 bits per R,G and B to 5 bits - the colour registers in OCS/ECS are already 16bit wide, but only 12bit are used.

Jay Miner was actually predicting exactly this (16bit colour) for a 1990 Amiga ... that would never come.

[hammer]

Originally Posted by Gorf

Not necessarily a new adapter, but just a fast-path to the existing DAC/Vidiot would be sufficient...

There was no fast enough DRAM in 92/93 to saturate such a bus:

Fast DRAM of that time was rated "70ns" or "60ns", which leads to a total roundtrip time of 120-140 ns, which is equivalent to a frequency of 7-8 MHz

---

FPM DRAM implements an improvement on conventional DRAM in which the row address is held constant while data from multiple columns is read from MDR using several column addresses.

The data held in the MDR form an open page that can be accessed relatively quickly, what speeds up successive accesses. This mechanism is known as burst mode access, and permits a block of (typically) four sequential words to be transferred from/to the memory bank. The first word takes the same time as conventional DRAM, however the subsequent three words are transferred faster.

This can be modelled with the time access form: x-y-y-y. FPM DRAM usually has an access time of 5-3-3-3 (5 cycles to the first access and the subsequent three take 3 cycles each), with speeds of 60 to 80 ns (for the first access) and a maximum bus rate of 66 MHz.

Tseng ET4000/W32i uses Fast Page DRAM(e.g. 70 ns), a memory clock of 50 Mhz, core of 86 Mhz e.g. https://www.vgamuseum.info/index.php...ng-et4000-w32i

60 ns translates into 16.6 Mhz.
70 ns translates into 14.2 Mhz.

For 70 ns, 14.2 Mhz effective x 3 cycle access needs a 42.6 Mhz memory bus which Tseng ET4000/W32i's 50 Mhz memory clock covers. 14.2 Mhz effective x 32-bit bus is 56.8 MB/s.


-------
3DO has its zealots.
[ Show youtube player ]
3DO has its OpenLara port. Software sells the hardware... 3DO missed it.

[hammer]

Originally Posted by Gorf

It would ave been also straight forward to go from 4 bits per R,G and B to 5 bits - the colour registers in OCS/ECS are already 16bit wide, but only 12bit are used.

Jay Miner was actually predicting exactly this (16bit colour) for a 1990 Amiga ... that would never come.

I would keep the original Los Gatos Amiga team as the advance R&D team and cull somewhere else.

[Gorf]

Originally Posted by hammer

Tseng ET4000/W32i uses Fast Page DRAM(e.g. 70 ns), a memory clock of 50 Mhz, core of 86 Mhz e.g. https://www.vgamuseum.info/index.php...ng-et4000-w32i

DRAM has no clock.
Whatever they mean by "effective memory Clock", they seem to have mixed up things on this page.
Tseng claims nothing alike in the original documents:
https://web.archive.org/web/20170228.../502285_DS.pdf

60 ns translates into 16.6 Mhz.
70 ns translates into 14.2 Mhz.

Please inform yourself how DRAM works before making such nonsense claims.
The numbers are the "random access time". That is how fast the DRAM chip will put a stored value at the data line after it is told the address.
But you need to wait the same time again, before you can ask for the next address.
(only when the next address is in the same column it can be much faster --> DoubleCAS)

Hence the "roundtrip time" is what you need to calculate the max frequency
And that is usually twice the access time!

So 60ns chips do have a roundtrip time of 120ns.

Tseng ET4000/W32i ...

maxes out at:

54.6 MB/s @ 1024x768x8, 72Hz

so nowhere near your claims of 200 MB/s

[hammer]

Originally Posted by Gorf

DRAM has no clock.
Whatever they mean by "effective memory Clock", they seem to have mixed up things on this page.
Tseng claims nothing alike in the original documents:
https://web.archive.org/web/20170228.../502285_DS.pdf




Please inform yourself how DRAM works before making such nonsense claims.
The numbers are the "random access time". That is how fast the DRAM chip will put a stored value at the data line after it is told the address.
But you need to wait the same time again, before you can ask for the next address.
(only when the next address is in the same column it can be much faster --> DoupleCAS)

Hence the "roundtrip time" is what you need to calculate the max frequency
And that is usually twice the access time!

So 60ns chips do have a roundtrip time of 120ns.



maxes out at:

54.6 MB/s @ 1024x768x8, 72Hz

so nowhere near your claims of 200 MB/s

http://gec.di.uminho.pt/discip/minf/...-Mem_Speed.pdf

---------------------------------

https://web.archive.org/web/20170228.../502285_DS.pdf
ET4000W32i has memory interleave page 13. Tseng Labs claims up to 70 percent performance increase instead of CPU's memory interleave of 20 to 30 percent. Tseng Labs claims VRAM-like performance.

Pixel workload is sequential in nature.

Page 15, Tseng Labs claims ATC can process 16-bit of display data at a rate of 50Mhz and 8-bit pixel data at a rate of 86 Mhz.


3DO VRAM has 20 ns access time which translates to 50 Mhz, hence 200 MB/s

https://3dodev.com/_media/documentat...l_guide_us.pdf
20 ns VRAM claim for 3DO.

3DO has two discrete buses i.e. 80 ns FP DRAM 32-bit wide and 20 ns VRAM dual 16-bit port. FP DRAM can't be used for frame buffer.

[Gorf]

Originally Posted by hammer

3DO VRAM has 20 ns access time which translates to 50 Mhz, hence 200 MB/s

https://3dodev.com/_media/documentat...l_guide_us.pdf
20 ns VRAM claim for 3DO.

3DO has two discrete buses i.e. 80 ns FP DRAM 32-bit wide and 20 ns VRAM dual 16-bit port. FP DRAM can't be used for frame buffer.

It is technically incorrect to speak of "access time" for the serial port side of VRAM. This is more correct the serial clock timing or the speed data is shifted by the internal shift register of the VRAM chip.

This timing ignores the time you need to setup a line for the serial output.

And of course this access is restricted to sequential reads:
so technically this behavior is no RAM as it provides no Random Access.
(we could call it LAM for Linear Access Memory)

But yes: VRAM does have a very high max throughput within these restrictions - that is why it was used in so many video cards and consoles.

One additional drawback of VRAM is the need for twice as many data pins per chip and therefore twice as many traces on the board.

So with almost the same number of traces and pins you can have a 64bit wide DRAM instead of a 32bit wide VRAM configuration.
And that's why VRAM died with the appearance of EDO-RAM and SDRAM.

[lionagony]

Originally Posted by hammer

I would keep the original Los Gatos Amiga team as the advance R&D team and cull somewhere else.

Yes, this is the single factor that would have made this thread moot. The original team prioritized over everything else and Jay Miner having better health would to me have changed everything and most likely led to another Amiga revolution around 1990-ish.

[TEG]

Originally Posted by lionagony

Yes, this is the single factor that would have made this thread moot. The original team prioritized over everything else and Jay Miner having better health would to me have changed everything and most likely led to another Amiga revolution around 1990-ish.

The other factor is the bleed of engineers following Jack Tramiel departure in 1985. Among them, Shiraz Shivji who seems to be a second Jay Miner judging by what he managed to do at Atari.

The clash with Jack was definitely the start of the end for Commodore. Not that Jack should have stay but how is departure happened was a definite shockwave for the company and so probably for the computers industry as we know it today.

[sokolovic]

A second Jay Miner ? He made the Atari ST

[TEG]

Originally Posted by sokolovic

A second Jay Miner ? He made the Atari ST

You're a bit harsh

[haps]

The simple fact of the matter is that commodore was mismanaged. Does not matter what sort of statistics and other bullshit you bring up, At the end of the day those in charge dropped the bundle and fucked up.

[TEG]

Originally Posted by haps

The simple fact of the matter is that commodore was mismanaged. Does not matter what sort of statistics and other bullshit you bring up, At the end of the day those in charge dropped the bundle and fucked up.

Yeah but that's seeing the world in B&W. Sometime the day can be very very messy and chances to deliver the bundle being near zero. So the discussion to try to evaluate how it was possible to success.

[grelbfarlk]

They should have incorporated a commercial butter churner into the A1200.

The Milky FJ55C Electric butter churn is a high-quality, very durable unit that is suitable for commercial use. It is ideal for small to medium farms and butter making businesses. This unit has a capacity of 55 liters (14.5 gallons), but the maximum cream load should not exceed 25 liters (6.6 gallons). The minimum cream load is 10 liters (2.6 gallons). The butter making cycle takes 20-35 minutes and has a 32%-42% butter output from the cream.

FEATURES:

• Made of stainless steel
  
• High quality motor with speed regulator
  
• Security switch
  
• Butter milk outlet
  
• Cold water inlet
  
• Water layer
  
• Power of motor: 750 W
  
• Power supply: 115v/60Hz

Or at least:
Clock Speed of Video Memory (RAMDAC)
800MHz
Maximum 2D Resolution (at 32-bit color)
Up to 2560 x 1600
Maximum 3D Resolution (at 32-bit color)
Up to 2560 x 1600
Megapixels/Megatexels
4.8 Gtextels/sec.
Supports MPEG-1, 2 Yes
TV-Out Yes
Stereo Sound No
DVD Decoding Yes
S-Video Output Yes
Video Format
MPEG-1, MPEG-2, MPEG-4, DVD, HDTV

A multi-stage grain drying system of a combine harvester comprises an air blower, a heat exchanger, a starting and generation all-in-one machine, a vehicle-mounted battery, a lifting auger, far infrared heaters and a grain collecting box, wherein the heat exchanger is installed on an exhaust pipe of an internal combustion engine, an air inlet end of the heat exchanger is connected with the air blower, an air outlet end of the heat exchanger is connected with a hot air pipeline, one branch of the hot air pipeline is connected with the lifting auger, the other branch of the hot air pipeline is connected with the grain collecting box, the lifting auger is provided with a first-stage far infrared heater, the middle of the grain collecting box is designed to be of a throat shape, a second-stage far infrared heater is installed in the center of the throat, and the first-stage far infrared heater and the second-stage far infrared heater are connected with a front inverter, a rear inverter, the vehicle-mounted power battery and the starting and generation all-in-one machine through connecting lines. The multi-stage grain drying system of the combine harvester is directly embedded into a work component of the combine harvester, directly dries grains in the combine harvester, and has the advantages of being simple in structure, being low in cost and saving energy.

The multistage grain drying system of a kind of combine, comprise fan blower 1, heat exchanger 15, starting-generating all-in-one 4, inverter, on-vehicle battery 6, promote screw feeder 9, far-infrared heater, receipts tanker 11, it is characterized in that, heat exchanger 15 is arranged on the blast pipe 2 of combine internal combustion engine 3, the inlet end of heat exchanger 15 is connected with fan blower 1, the termination hot air duct 14 of giving vent to anger of heat exchanger 15, a branch road of hot air duct 14 is connected with lifting screw feeder 9, cereal charging aperture 13 is located on this branch road, and tanker 11 is received in another branch road access of hot air duct 14; Promote on screw feeder 9 one-level far-infrared heater 12 is installed, the outlet that promotes screw feeder 9 is located at the top of receiving tanker 11, the middle part of receiving tanker 11 is designed to aditus laryngis shape, and secondary far-infrared heater 10 is installed by the central authorities of aditus laryngis, forms a narrow annular annular channel with aditus laryngis; One-level far-infrared heater 12 is connected with front inverter 5, vehicle mounted dynamic battery 6, rear inverter 7, starting-generating all-in-one 4 by being connected electric wire 8 with secondary far-infrared heater 10, and starting-generating all-in-one 4 is connected with combine internal combustion engine 3.