04 March 2023, 16:13 | #241 | |
son of 68k
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Quote:
It needs verification, but i think it is really 5 for rotates and 6 only for shifts. |
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04 March 2023, 17:10 | #242 |
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They're all 6-bit (it was tested on real hw, a500 68000): they all take tbe same number of cycles.
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04 March 2023, 17:13 | #243 |
Alien Bleed
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Being able to shift 6 bits makes sense if you are thinking of some future 64-bit wide register implementation. Although that probably wasn't the actual reason.
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04 March 2023, 17:18 | #244 |
son of 68k
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Only logical reason is ability to shift by 32. With 5-bit, range is only 0-31.
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04 July 2023, 07:56 | #245 |
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06 July 2023, 07:40 | #246 | |
son of 68k
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Quote:
Actually, it is of course 9, 17 or 33 bits depending on the size. One could think it is logical to cut at 6-bit for .l, 5-bit for .w, 4-bit for .b, but it's not what the cpu does - it's always 6 regardless of the operand size. Note that PowerPC uses 6 bits as well, but not x86 (didn't check though, this is what i've read). |
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06 July 2023, 09:58 | #247 |
Defendit numerus
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From this page: https://c9x.me/x86/html/file_module_x86_id_273.html
it seems that starting from Intel 286 processor, the rotation is masked to 5 bits. and the masking is done in all operating modes, including the virtual-8086 mode (see note at the bottom of the page). EDIT: of course the same for shift instructions (https://c9x.me/x86/html/file_module_x86_id_285.html) I've written code for x86 several times, in a distant past, but never bothered about it and probably never considered it. Nice sh*t... But we are off-topic Last edited by ross; 06 July 2023 at 10:05. |
17 September 2023, 11:07 | #248 |
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Based on this 6502 routine:
Code:
;Divide by 24 for 6502 CPU ;15 bytes, 27 cycles lsr lsr lsr sta temp lsr lsr adc temp ror lsr adc temp ror lsr Code:
; divide by 24, no rest, no overflow lsr.l #3,D0 move.l D0,D1 lsr.l #2,D0 addx.l D1,D0 lsr.l #2,D0 addx.l D1,D0 lsr.l #2,D0 Code:
; divide by 3, no rest, no overflow move.l D0,D1 lsr.l #2,D0 addx.l D1,D0 lsr.l #2,D0 addx.l D1,D0 lsr.l #2,D0 Not tested, but seems to be OK. |
17 September 2023, 13:20 | #249 |
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Here is divide by 3 with rest:
Code:
; divide by 3 with rest, no overflow move.l D0,D1 lsr.l #2,D0 addx.l D1,D0 lsr.l #2,D0 addx.l D1,D0 lsr.l #2,D0 ; score sub.l D0,D1 sub.l D0,D1 sub.l D0,D1 ; rest |
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