68030 Architecture - RAM and A30

[jasonsbeer]

General question about the 68030...

Specifically, I am looking at the RAM access PAL equations on page 12-20 and figure 12-9 of the 68030 user manual. A30 plays some significant role in RAM access, but I can find no mention of its role in the text. It is always logic high in the presented use cases and this is called out in the equations. I'm curious if anyone can explain the role of A30 in this context.

Here's a link if you are curious as well...https://www.nxp.com/docs/en/referenc.../MC68030UM.pdf

[alexh]

I *believe* it is application specific.

In one example in this PDF (Figure 12-13) A30 is used to generate /STERM (Synchronous Bus Cycle Termination)

[Thomas Richter]

Originally Posted by jasonsbeer

G
Specifically, I am looking at the RAM access PAL equations on page 12-20 and figure 12-9 of the 68030 user manual. A30 plays some significant role in RAM access, but I can find no mention of its role in the text.

There is nothing specific about A30 for the 68030. Just that in this particular application, the RAM is placed at 0x40000000 such that A30 is used to address it. Note that for typical 68K installations, you have ROM from 0 upwards to have the autovectors available upon bootstram, so this is a (partial) system where you would have ROM in the first 1GB and RAM in the 3rd GB.

[jasonsbeer]

Originally Posted by Thomas Richter

There is nothing specific about A30 for the 68030. Just that in this particular application, the RAM is placed at 0x40000000 such that A30 is used to address it. Note that for typical 68K installations, you have ROM from 0 upwards to have the autovectors available upon bootstram, so this is a (partial) system where you would have ROM in the first 1GB and RAM in the 3rd GB.

OK. That helps. I appreciate your reply!