02 January 2022, 03:04 | #1 |
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Join Date: Feb 2018
Location: Milwaukee / USA
Posts: 4
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Bridgette/A4000 problem and Understanding _BRIDGE signal
Hey all,
I'm currently working on a 4000TX that is failing the chip ram test w/ diagrom consistently. For anything written, only the two MSBs are read back correctly, the two LSB/low word returns all ones. So D0-D15 are fubar in chip ram, but rom and custom chip regs are fine. Looking at signals on the scope it seems like all is well on the unbuffered side of the data bus (d31-d16 look similar to d15-d0) - albeit not with 100% confidence as there's lots of artifacts as things come on and off the bus. Looking at the chip ram, the low bytes definitely seem to be strange- in comparison to the clean signals on the high bytes. RAS/CAS/OE/WE signals track. There's not a lot on this half of the buffered data bus that could do this. Paula and Alice, and of course Bridgette. Paula must be at least good for writes, since I have serial output, but I don't know how it's selected exactly, just that RGA and the clocks are qualifiers. So I read the Bridgette description on page 6-16 in the A4000 Hardware Addendum expecting to find byte-wise or word-wise controls for bridging the processor and chip bus, but this is not the case- it's all or nothing bridge, which the exception of a strange mode that bridges the chip ram data bus halves together. This is activated when _BRIDGE aka _CBR is active. This mode is indeed in play during the chip ram test, which leaves me wondering wtf the point of this mode is and if there's some weird behavior on the processor side of the bus during this mode which is corrupting my reads. Anyway. TL;DR: - Have a 4000 with the low word returning all ones in chip ram, high word working fine. Any thoughts? - Possibly related: What is the purpose of the chip ram <-> chip ram bridge mode that can be activated in Bridgette? Thanks all, I realize this is a bit esoteric. : |
18 January 2022, 05:23 | #2 |
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Join Date: Apr 2021
Location: Ventura, CA, US
Posts: 14
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Check that your GALs at U212 and U213 do not have loose connections?
It is possible that U216 is problematic? I am building an ACILL a4000 board, and I ran into a similar (but not exactly the same) behaviour. I pushed down on the GALs, which revealed a loose connection. I also replaced U216, which was erratic, too. bob |
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