Chip RAM handling

[AlexBruger]

Hi everyone, I'm currently trying to figure out how Chip RAM is handled in the classic Amigas (500/2000).

Here is the information I have gathered so far:
I’ll refer to the different versions of Agnus as Ag512K, Ag1M and Ag2M depending on their DMA-Pointer width.

There is the CPU Address Bus and the Agnus Address Bus.
The CPU Address Bus can address directly Fast RAM and some Chips, like the CIAs.
The CPU Address Bus is fed into Gary (A17-23) and Agnus.
Ag512K and Ag1M have the inputs A1-A19 and Ag2M has an additional A20.
The input A19 may be changed to A23 via the jumper JP2/J101, which is only useful for Ag512K and Ag1M.

Ag512K and 1M act very similar, they both use the input A19 to select the memory bank via RAS0/1 and they both use a multiplexed address bus with 9 bit to choose the memory cell.
The only difference between them is that the Ag512K has a DMA-Pointer with 18 bit and the Ag1M has a DMA-Pointer with 19 bit.

Ag2M is a different beast and has a multiplexed address bus of 10 bit making the memory banks unnecessary, since it can address now the full 2 MB directly.
So there is no bank selection via RAS anymore.
It also has an DMA-Pointer with 20 bit.

Gary usually activates the RAMEN signal when the address is between 000000 and 020000.
But there is an input EXRAM which causes it to activate RAMEN also for C00000-D80000.
This input can be connected to the Trapdoor Connector or set to GND via a second jumper JP7A/J500.

So here is where I’m confused:

I assume that the 19th bit of the Ag1M DMA-Pointer is used for memory bank selection via RAS0/1 as well.
I haven’t found any hard evidence for this though.

1. What’s the purpose of mapping the second 512K to C00000.
   I would assume that for the Ag512K it would be treated as Pseudo-Fast-RAM even if it’s at 80000, since it can’t address it.
   And for Ag1M, what’s the point of making it Pseudo-Fast-RAM when you can have Chip-RAM.
2. Which brings me to my second question. Why does mapping it to C00000 with a Ag1M make it Pseudo-Fast-RAM at all?
   Since A1-19 are only inputs (not outputs) and the Multiplexed Address Bus is not connected to Gary neither Gary nor the setting of JP2/J101 can have an impact on the addresses generated by Agnus itself.
   So shouldn’t Agnus be able to access what the CPU knows as C00000 at 80000 making it Chip-RAM again (a weird one, but still)?
3. According to some source (e.g. Abacus Amiga System Programmer's Guide) if you have only 512K DRAM installed you will have mirrors of 000000-07FFFF at 080000, 100000 and 180000 (from CPU perspective).
   Obviously not right for Ag2M but for the other ones doesn’t that mean that RAS1 would have to be rerouted to trigger memory bank 0 as well?
   Looking at schematics I have available I see that you can switch the RAS Signals with the jumpers JP3 but it doesn’t look like they are used to reroute both to RAS0.
   Although the A1000 schematics seems to support that. Is this only true for A1000?
   For A500/A2000 I would expect a mirror at 100000 only.
   Some tests in WinUAE seem to suggest that there is in fact a mirror at 80000.
4. Also what happens if you access 080000 when you only have 512K DRAM and RAS1 would select the empty memory bank 1 (Ag500K/1M). Does this cause a Guru (Bus Error) or just 0 on the data bus?
   Or similar Ag2M access to address outside the installed DRAM range, e.g. 100000 with 1 MB installed.
5. And final question how does the operating system determine how much memory is available.
   The hardware doesn’t much care, it tries to access at the location you tell it to, but the OS knows exactly how much memory is where available, how does it do that?

I know a lot of questions, but I tried hard to find the answers myself without any luck, so I hope people with more practical experience can answer them.
Thanks
Alex

[Jope]

Some quick thoughts:

1. It's not as much about the Agnus as it is about the OS marking it as Chip RAM and then making a mess of things when software tries to use the "second 512k of Chip" that the 512k Agnus can't actually use as Chip RAM. Blitting around things in the wrong block of RAM and so on.

2. It is pseudo Fast because it is on the Chip RAM bus, thus any custom chip DMA will inhibit the CPU's access to the C00000 RAM.

4. You will either get bus noise or mirrored contents if you access non-existing RAM.

5. Check the 1.2 exec disassembly for a general idea on how it's detected. These detection routines were revised for 1.3 and later OSes, but as said, the general idea is there. http://wandel.ca/homepage/execdis/exec_disassembly.txt

[hooverphonique]

Regarding 2. I think it is usable as actual chip ram, but the OS will not allocate it as such because it is detected (via cpu) to sit at C00000, thus addresses in this range will never be used as custom chip DMA pointers. You could of course do this deliberately, if you wanted to.

[AlexBruger]

Thanks for the quick answers.

Interestingly it seems to be "because of the OS" for most of my questions.
But it makes of course perfect sense.

Thanks for the link to the commented disassembly of exec.
This is a goldmine. After taking a quick glance it seems that the detection is dealing heavily with mirrored memory as well, so maybe I can find the answer to my 3rd question in there.

[Fastdruid]

Not answering any of the questions but on #1, I don't know why but this is also called "Ranger" RAM. AIUI there is a theory that this was the address space intended for VRAM and there because of the code named "Ranger" project which was Jay Miners version of the A2000 before Los Gatos was closed.

[Jope]

Originally Posted by hooverphonique

Regarding 2. I think it is usable as actual chip ram, but the OS will not allocate it as such because it is detected (via cpu) to sit at C00000, thus addresses in this range will never be used as custom chip DMA pointers. You could of course do this deliberately, if you wanted to.

With a 1MB Agnus, you can indeed leave it in 512/512 mode and load stuff to the Slow RAM, then use it as Chip RAM. The OS will of course refuse to do this. This was recently discussed in another thread, the ACA500+ does this trick for you by doing an address line swap in hardware so that the C00000 RAM looks like Chip RAM to the CPU. The Agnus doesn't really care either way, it's the same signaling as far as it is concerned internally.

[AlexBruger]

So based on the feedback I have create the following graphic:




And this are the 2 memory detection routines from exec in c-like pseudo code:

int GetAmountOfChipRam()
{
  memory[0]=0;
  const int signature = 0xF2D4B698;
  for(int i=0x1000; i<0x20000; i+=0x1000)
  {
    memory[i]=signature;
    if (memory[0]!=0) return i;
  }
  return i;
}

int GetAmountOfPseudoChipRam()
{
  const int step = 0x40000;
  for(int i=0xC00000; i<0xDC0000; i+=step)
  {
    // Write to RAM or INTENA (0x1000-0xF66 = 0x9A)
    // If it is INTENA we disable all interrupts
    memory[i + step - 0xF66]=0x3FFF;
    
    // Read from RAM or INTENAR
    if (memory[i + step - 0xFE4] == 0)
    {
      // When 0 it may still be RAM or INTENAR
      
      // Try to set all interrupts, except master interrupt enable
      memory[i + step - 0xF66]=0xBFFF;
      
      // Read again INTENAR
      if (memory[i + step - 0xFE4] == 0x3FFF)
      {
        // Now we can be sure that we are manipulating Chip Registers
        
        // Disable all interrupts
        memory[i + step - 0xF66]=0x7FFF;
        return i - 0xC00000;
      }
    }
  }
  return i - 0xC00000;
}

My assumption would now be that the detection routines would report too much memory in the configurations with bus noise since they rely on mirroring.