23 March 2021, 22:58 | #81 |
Retired Quartex Sysop
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I have nothing but respect for the talents you designers are showing.. wish we had this back in the day too....
More memory than 1Mb though maybe? |
24 March 2021, 16:48 | #82 |
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Maybe, yes. One of the nice things about this (and the original design) is the simplicity of the design. Adding 1Mb @$C00000 was easy as I only needed 3 extra logic IC's. There is room at that address range for up to 1,75Mb though.
So a future version could have more memory. For even more memory we would have to move to Zorro II space but that requires a lot more logic. This accelerator should be seen as a "moderate" accelerator. Just enough to play the upcoming dread at a higher framerate or prevent any slowdowns when you "nuke" 100 Lemmings. |
24 March 2021, 22:27 | #83 |
mä vaan
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this looks nice and simple. If it works, I would like to get one, if possible.
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25 March 2021, 08:34 | #84 |
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25 March 2021, 16:13 | #85 |
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Is there a version of this which just gives the 14Mhz increase with no fastRAM and no IDE?
I know some will say it does not make sense, however there are expansions that already provide just fastRAM and IDE. With this they could possible now have a 14MHz improvement. |
25 March 2021, 17:34 | #86 |
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The board I designed could also be build without the fast ram. It's just a matter of leaving some components out and making 2 jumpers.
But you know what I'm going to say.. Without fast ram that also runs at 14MHz the speed gain would be very, very minimal. If you already have a fast ram / ide expansion and you stack this card on top of it than the fast ram will still run at 7MHz hence there will no be speed improvement. |
25 March 2021, 18:25 | #87 | |
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Quote:
I woun't be able to build this myself. Last edited by utri007; 25 March 2021 at 21:24. |
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25 March 2021, 19:37 | #88 |
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25 March 2021, 19:41 | #89 |
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25 March 2021, 19:46 | #90 | |
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Having a real cache is possible but needs more logic. And that would mean GAL's or CPLD's and that takes away the charm of this little accelerator. |
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25 March 2021, 20:50 | #91 |
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26 March 2021, 07:58 | #92 | |
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Quote:
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30 March 2021, 18:51 | #93 | |
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Awesome
Quote:
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30 March 2021, 21:16 | #94 | |
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Quote:
So then I needed a relocator to fit it better in my 500. And why not add a clock doubler on that relocator. That didn't go as well, since I followed the schematics by the first poster. I thought there were a few strange things, and I did compare with the schematics by Livio Plos, but I thought nah, I'm just imaging. If yours work, I'd be very grateful if you could share your schematics. Crappy picture attached. If anyone is wondering, they are both 4 layer boards. I could probably have done the relocator on 2 layers. The RAM board probably not at that size. Also I like signal integrity |
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31 March 2021, 20:54 | #95 | |
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And yes, I will share the design as soon as I've confirmed it works! |
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01 April 2021, 12:23 | #96 | |
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I'm somewhat experienced at drawing PCBs, much less experienced with Amiga and 68k stuff. So I don't know if there could be any issues not using the bus arbitration signals in this design. It's faster (1.37 times A600 according to SysInfo) and I haven't noticed anything glitchy yet. I'm hoping I can pop it onto the 14 MHz board and it will just work |
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01 April 2021, 12:44 | #97 | |
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Quote:
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05 April 2021, 08:01 | #98 |
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A little update with some good and some bad news.
The PCB's I ordered are in and they look good. They also fit quite nicely. There will be no need for a relocator board and the metal shield will fit just fine. I have begun with testing the clock doubler. This version has a 7->14MHz clock doubler based upon an old-skool 74HCT4046 PLL. So, there is no need for a patch wire to Gary to feed in the CDAC clock. This is a standalone plug&play board. But, anyone who ever designed PLL's knows they can be quite temperamentful . In this case the PLL wouldn't lock because of a fundamental mistake in the loop filter I designed (the loop bandwidth was way too small). So I corrected that and that got me a nice 53% duty cycle 14MHz signal right out of the box. However, the falling edge of the 14MHz clock was jittering. It turned out this was caused by the signal level of the Amiga's 7MHz clock that doesn't swing completely to 5V. Apparently this mis-biased the PLL's input amplifier causing jitter. By capacitively feeding the 7MHz clock into the 74HT4046 this was resolved. The clock is still a tiny bit jittery but not enough to cause any problems I think. So, the bad news is that the PCB needs a patch to add the coupling capacitor and make it work. However, it is just a tiny patch and once the rest is working I will release fiixed gerbers, schematic, etc. EDIT: Will post some scope screens if I have some time. Duty cycle is close to 50% and there is about 15.25ns delay between the 7MHz and the 14MHz signal. The delay is a tiny bit high but yeah, the HCT4046 is not terribly fast.. I'll see how it goes when the rest of the circuit is up and running. EDIT2: scope screenshot: . Delay is less than estimated, just 18ns. I also made a final tweak to the loop filter and now the jtter is 2ns peak-peak. Duty cycle can be made 50% by tweaking a resistor value. Last edited by Mathesar; 05 April 2021 at 10:04. |
15 April 2021, 21:59 | #99 |
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Quick update, i have assembled the board without the fast ram to test the cpu/clock doubler.
Unfortuntely it doesn't work properly yet. AS/DTACK and E/VPA/VMA timing looks great but somehow the boot process stops after the first drive click and I am left with a white screen. It looks like the cpu is then halted and only processes interrupts. It does boot into chucky's diagrom though. Graphic/sound/keyboard all works fine. Memory test I don't understand fully (shadowram?) but what really goes wrong is cia test and drive tests. Cia's run too slow according to the test (especially the hsync one) and sometimes the system even crashes on that part. Now, at this point I am suspecting interrupt timing. Interrupts might be sampled too early by the 14mhz cpu and triggering the wrong interrupt levels. Does this make sense? |
15 April 2021, 22:17 | #100 |
ex. demoscener "Bigmama"
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How does the generated E-clock relate to the orignal 7MHz clock as compared to a standard amiga?
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