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Old 21 May 2008, 16:39   #22
Toni Wilen
WinUAE developer
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 46
Posts: 24,746
New logic analyzer findings (it has been too long..)

I finally decided to snoop RGA (custom register address bus) bus. Should have done this ages ago but I was stupid and too lazy

RGA = custom address accessed, WE = write enable, INT3 = Agnus int3 pin, DMAL = Paula DMAL pin (not used yet), IPL = CPU interrupt level.

Guess whats happening in these images? (hint in image names)

Apparently every custom chip number is directly available in RGA bus, even if it is Agnus internal register. (RGA is used to transfer data to/from Denise and Paula, for example Agnus bitplane DMA puts BPLxDAT to RGA and does DMA from chipram)

This means blitter line mode cycle diagram mystery will be finally solved in few days.

EDIT: delay between bltsize and first DMA transfer looks interesting and is quite long..
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Last edited by Toni Wilen; 21 May 2008 at 18:35.
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