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Originally Posted by robinsonb5
Isn't data cache disallowed for Chip RAM though? (The CPU reading data that the blitter or disk DMA has written gets way more complicated if there's a data cache.)
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I presume so, but testing in FastRAM revealed negligible difference between data cache on and off, perhaps because in this program the data spends most of its time in registers.
Even if the data was being written to ChipRAM, some accelerator cards (including the Blizzard 1230-IV?) have a 'delayed write' feature that starts a ChipRAM write and then disconnects the local bus so the CPU can continue processing, only waiting if it has to access ChipRAM again before the write has finished.
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That's interesting - can you compare an "easy" screenmode, like PAL 16 colours with, say fully overscanned DblPAL in 256 colours?
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My previous tests were done on a PAL screen with 8 colors. I couldn't get full overscan to work in DblPAL, so I set it to 676x454 (max text overscan) in DblNTSC. Running litwr's V4 code the results were:-
FastRAM, 256 colors, CPU caches on: 10.1 seconds
ChipRAM, 16 colors, CPU caches on: 15.2 seconds
ChipRAM, 256 colors, CPU caches on: 44.4 seconds
ChipRAM, 16 colors, CPU caches off: 61.2 seconds
ChipRAM, 256 colors, CPU caches off: 194.3 seconds
From this we see that when running from chip - even with massive DMA contention - having CPU caches on makes a huge improvement. When running max text overscan in 256 colors it was 4.4 times faster with caches on. In 16 colors it was 4.0 times faster.