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Just a remark regarding the DRAM chips: 256k x 16 (4Mbit) are sufficient to build a 2MB expansion with 4 chips. Examples are IS41C16256 or M11B416256A. They are available in 40pin SOJ packages.
My idea for the Gary adaptor: If you make Gary 'see' $C00000 by separating it from the address bus with logic chips, you can expect it to generate the same signals every time memory locations are accessed where the 2MByte expansion resides. For that you'd only need 4 address pins and maybe a clock signal to avoid glitches.
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