Quote:
Originally Posted by Kalms
Aha. That I do not know, sorry, and never looked into because:
The 68000 CPU instruction set is designed so there never are any instructions that take an odd number of cycles, or start a memory access at an odd number of cycles.
I believe that a 68000 memory access that gets delayed by the Amiga chipset always gets delayed by an even number of cycles (I.e. to the beginning of the Nth following DMA slot).
Because of the above, I believe there is no way for the CPU to become desynchronized in the way that you outline above. Except, if you manipulate DTACK via homemade hardware then -- hmm, no, sorry, no idea what would happen then.
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Yeah, it's probably completely academic — I was thinking of hypothetical cases of e.g. a Zorro device with one-wait-state memory on it, or one that did something other than VPA for interfacing a lower-speed component.
I can think of no way that the 68000 could get out of phase in a stock Amiga, as all exceptions seem to fire at two-cycle boundaries, all instructions (including TAS and variable-length multiply and divide) are multiples of two cycles in length, and all peripheral chip accesses retain alignment.