Thank's for the answer.
I see the different results between 4.4 and 4.9
First to the wait-command:
The wait-command needs for me now 4 copper-cycles or 8 CCKs.
"so each of the waits end up taking 8 CCKs
(3 normal cycles: 2 to read copper instructions, 1 for wait to finish and one "wasted")."
Code:
[38 56] [39 57] [3A 58] [3B 59] [3C 60] [3D 61] [3E 62] [3F 63]
COP 08C COP 08C
0 3033 FFFE W
0007180C 0007180C
99E1CC00 99E1CE00 99E1D000 99E1D200 99E1D400 99E1D600 99E1D800 99E1DA00
; <IR1> <IR2> <sleep start> (sleeping) <wakeup> (next instruction's IR1 fetch).
$38 - IR1 (fetch) ; copper-cyle 1
$3A - IR2 ; copper-cyle 2
$3C - sleep start ; copper-cyle 3 - wasted - First refresh cycle is cycle 3
$3E - wakeup ; copper-cyle 4
then
$40 - IR1 (fetch) again ; copper-cyle 1
2. bitplane-DDFSTRT:
DDFSTRT does not equal first bitplane slot. When DDFSTRT matches horizontal position,
it takes 4 cycles more before first bitplane slot is selected (plane 8) because
bitplane enable has multiple stages and internal RGA bus is pipelined.
Code:
DDFSTRT on $38
[38 56] [39 57] [3A 58] [3B 59] [3C 60] [3D 61] [3E 62] [3F 63]
1 2 3 4 - BPL4 BPL6 BPL2
(free) (free) (free) (steal)
99E1CC00 99E1CE00 99E1D000 99E1D200 99E1D400 99E1D600 99E1D800 99E1DA00
[40 64] [41 65] [42 66] [43 67] [44 68] [45 69] [46 70] [47 71]
COP 08C BPL3 BPL5 BPL1
(free) (steal)
Is my interpretation correct?
3. move-command:
Code:
[30 48] [31 49] [32 50] [33 51] [34 52] [35 53] [36 54] [37 55]
COP 08C COP 180
0180 0444
00071808 0007180A
99E1BC00 99E1BE00 99E1C000 99E1C200 99E1C400 99E1C600 99E1C800 99E1CA00
But why starts the copper-move on $34 and not on $30 by a wait on dc.w $3031,$fffe?
All following copper-moves have two copper cycles. Only the first one not.
(It's also a different between 4.4 and 4.9)
Code:
[38 56] [39 57] [3A 58] [3B 59] [3C 60] [3D 61] [3E 62] [3F 63]
COP 08C COP 180 COP 08C COP 180
0 0180 0555 0180 0666
00073F44 00073F46 00073F48 00073F4A
EEAA2400 EEAA2600 EEAA2800 EEAA2A00 EEAA2C00 EEAA2E00 EEAA3000 EEAA3200