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Just picking up on some of the questions above:
- SDIO IDE performance will not improve much as Gayle emulation because the bottleneck is the motherboard bus (not that I can remember where we were with numbers, but there isn't really anything to optimise there). Where it could be improved is with the addition of a DMA-capable mode (with driver obviously). This won't be there on launch but my intention is that it will be possible to update the FPGA bitstream without any special tools.
- Level shifters are underneath. There is no skimping on the design. It's an 8-layer board with double-sided SMT.
- The serial bus is underneath on an FFC connector. It is differential and has three data pairs and one clock pair. It's mainly for my own dev use but you never know.
- Release date - realistically I think January. There is a slim chance it could be ready before but I still have some more work to do on the logic and I'm pretty busy right now. There are also supply-chain problems in the industry at the moment with long lead times on a lot of components and the stocking disties out of stock of many parts. I haven't checked if anything on this is affected yet.
- Pricing - waiting on quotes from the assembly house. Will update soon. I do need to try to get a handle on levels of interest so once I have prices I will set up some sort of registration page.
Regarding open-source: As I've said before it will not be fully open source at least from day one because of the significant NRE cost that needs to be recouped. I would expect to release a subset of the HDL at some point, and possibly all of it eventually. Clearly this board would make a nice general purpose, 5V tolerant, breadboardable FPGA dev board so if there is interest for "alternative uses" that can be factored in to my volume estimates then please let me know.
Mike
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