Quote:
Originally Posted by bloodline
At step two the CPU is loading a value from memory into a Dx register... at step two the Copper is loading a value from memory into a Custom chip register.
To follow your model, the Custom Chip registers are the Copper's registers.
The copper cannot write to RAM, if it needs to do so, then it needs to do that with the blitter, by setting the blitter registers.
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Oh that is a really good explanation of how to view it! Thank you!
Quote:
Originally Posted by bloodline
No, there are 8 DMA slots per 16 lores pixels. These 8 DMA slots constitute a bitplane fetch cycle.
1bit graphics only uses one of those slots per fetch cycle, which leaves 7 slots free per fetch cycle.
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I never grasped that HRM illustration completely. Also their -2, -1, 1, 2,... numbering below confuses me because it lacks zero.
So my question is when using 4 bitplanes lo-res: bitplane dma uses all odd cycles because 4-2-3-1 are interleaved: Does that mean Copper is completely stopped during the 320 visible pixels portion? Since only Blitter and CPU are able to utilize even cycles?