Quote:
Originally Posted by PeterK
But what happens when you read word or long sequences from a not aligned memory block? Do you get a possible penalty only for the first read access, but then the following reads can re-use the previous data from the cache and only need to fetch the subsequent words or longwords from memory? Or is there still a cache read penalty?
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Cache lookups are performed on a (aligned) longword basis, so if your read operation straddles a longword boundary you'll have 2 cache lookups (each of which could result in a cache miss). Even if both longwords are in the same cache line you'll still occur a penalty. For 68060 it's 1 clock cycle (2 for RMW instructions), see MC68060UM 10.2.5. I'm not sure what the exact penalties are for 030 and 040 but the user manuals contain similar language.