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IFW · 25 June 2003, 16:36

An X86 has tons of registers... you just don't see them. Really.
1, a modern (p3+) x86 cpu hardware is using register renaming/aliasing to show the usual set of registers towards applications, but internally as long as it has a new register and an older one is being used, it dynamycally "renames" an internal register to another "visible" register if a new instruction is not using the results of the previous operation. All internal registers have busy statuses that the execution and feeding units use to decide which one and how to use.
As you can guess this is very complex, as the cpu must remember which renamed register holds the result of the execution of what instruction...!
2, To make this work x86 has out of order execution (instructions executed in almost an arbitrary order) for a very long time. Also branch prediction discarding results if an unpredicted branch is taken (based on runtime statistics by the cpu) etc.
3, Aside from this stuff, you want use the mmx, and other enhanced integer registers to simulate more registers, if you really need that. SSE2 is highly recommended as you get 128 bit integers freely accessible by the whole or in part (very useful for this purpose), but only from p4.
4, Actually a newer x86 is more risk like, than cisc...

If anyone is willing to pay for the work (this is very far from hobby programming) I am willing to make that ppc emulator. Please note it only really makes sense with p4 class cpus (sse2). Less is possible, but may be unusable for real time applications.

25 June 2003, 16:36	#9
IFW Moderator Join Date: Jan 2003 Location: ... Age: 52 Posts: 1,838	An X86 has tons of registers... you just don't see them. Really. 1, a modern (p3+) x86 cpu hardware is using register renaming/aliasing to show the usual set of registers towards applications, but internally as long as it has a new register and an older one is being used, it dynamycally "renames" an internal register to another "visible" register if a new instruction is not using the results of the previous operation. All internal registers have busy statuses that the execution and feeding units use to decide which one and how to use. As you can guess this is very complex, as the cpu must remember which renamed register holds the result of the execution of what instruction...! 2, To make this work x86 has out of order execution (instructions executed in almost an arbitrary order) for a very long time. Also branch prediction discarding results if an unpredicted branch is taken (based on runtime statistics by the cpu) etc. 3, Aside from this stuff, you want use the mmx, and other enhanced integer registers to simulate more registers, if you really need that. SSE2 is highly recommended as you get 128 bit integers freely accessible by the whole or in part (very useful for this purpose), but only from p4. 4, Actually a newer x86 is more risk like, than cisc... If anyone is willing to pay for the work (this is very far from hobby programming) I am willing to make that ppc emulator. Please note it only really makes sense with p4 class cpus (sse2). Less is possible, but may be unusable for real time applications. Last edited by IFW; 25 June 2003 at 16:53.