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Old 03 October 2021, 22:06   #3
Toni Wilen
WinUAE developer
 
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 46
Posts: 25,236
Copper WAIT cycle is:

<IR1> <IR2> <sleep start> (sleeping) <wakeup> (next instruction's IR1 fetch). Real total is 4 copper cycles. Internally wakeup cycle generates request for IR1 (due to pipelining IR1 DMA transfer happens in next copper cycle) so technically you could also say WAIT is 3 cycles even if it isn't the whole truth

Horizontal cycle origin was changed in 4.5+ betas. It was wrong previously. First refresh cycle is cycle 3. It is not cycle "-1". HRM lies. DDFSTRT does not equal first bitplane slot. When DDFSTRT matches horizontal position, it takes 4 cycles more before first bitplane slot is selected (plane 8) because bitplane enable has multiple stages and internal RGA bus is pipelined.

btw, W is back in DMA debugger, it was accidentally moved to wrong place when copper emulation was rewritten few times..
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