Quote:
Originally Posted by Thomas Richter
There is no "memory space" - there are only "large regions" that are allocated in 2MB chunks, or small regions that are allocated in 64K chunks, and the large chunks end up in the "memory region" and the small chunks end up in the I/O space. What board hardware probably does is to map only the I/O space as cache-inhibited, but that does not make any practical difference for the problem at hand because the CIIN-defect of the 68030 is present regardless of CIIN (well, that is the defect).
Side information: The GVP EGS 110 has no blitter, and thus can enable caching for video RAM. Thus, GVP added a "startup tweak" to be run before setpatch which added "dummy" memory regions into the exec memory list.
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Whether you prefer to call it a region or an address space really makes no difference. What is important to remember, is that for Zorro2 there are designated cachable and non-cachable address spaces. Zorro2 Fast memory expansions use the cachable address space and Zorro2 I/O expansions use the non-cachable address space.
For Zorro3 expansions, the are no designated cachable and non-cachable address spaces, each board or device determines it's cachable functionality.
BTW, I have a Picasso II+ which maps 2MB of graphics RAM into the Zorro2 cachable space. I would expect that, the blitter register is mapped into the Zorro2 non-cachable space. So, I don't know why P5 would do such sloppy design work when they had a proven good design example available in Germany.
