Hi Don,
Here are some hardware design considerations for code optimizing the IDE versions of scsi.device:
- 68020/68030 internally handle dynamic bus sizing more efficiently than most 040/060 CPU cards. This is one reason (but not the only one) why word transfers seem to give better performance with 040/060.
- The A4000 state machine logic terminates the cycle on the CPU side of the bus approx. 5 clocks before the IDE side of the bus terminates it's cycle. The idea is to free the CPU to perform some other task while waiting for the IDE bus cycle to complete. This is more friendly to the OS in terms of CPU usage but if the CPU commits to a longer bus cycle due to a slower task or accessing a slower port it can delay the start of the next IDE bus cycle (resulting in a slower transfer rate).
- The 040/060 have larger internal caches and improved instruction execution pipelines so they are more likely to complete tasks and be ready to begin the next cycle on the IDE bus (but they can still be delayed by accessing a slower external port) and another reason why word transfers may be seem give a better performance with 040/060.
As you can see there are performance trade offs with word vs. longword transfers and CPU usage vs. IDE max. transfer rate. I hope this can be of some help to you.
