I started to optimise/rework scsi device.
Three versions are available: for A600 (ROM 3.0+), for A1200 and for A4000 on:
New version is a few fastest, especially for slower CPU's. Also perhaps
Code:
;ReadWriteData MOVEM.L D2/D3,-(SP)
; MOVE.L D0,D2
; MOVEQ #0,D3
; CMP.B #4,D2
; BEQ.S WaitForReady
;lbC002F18 TST.B D3
; BNE.S WaitForReady
; MOVE.L $20(A5),D0
; JSR -$13E(A6)
;WaitForReady MOVE.B $1E-Modulo(A4),D0
; CMP.B #2,D2
; BEQ.S lbC002F34
; CMP.B #4,D2
; BNE.S lbC002F46
;lbC002F34 BTST #7,D0
; BNE.S WaitForReady
; BTST #0,D0
; BNE.S lbC002F4E ; error handler ???
; BTST #3,D0
; BEQ.S WaitForReady
;lbC002F46 MOVE.W lbW002F5C(PC,D2.W),D0
; JMP lbW002F5C(PC,D0.W)
;lbC002F4E MOVE.B 6-Modulo(A4),$277(A2)
; MOVE.W lbW002F64(PC,D2.W),D0
; JMP lbW002F64(PC,D0.W)
;lbW002F5C dc.w lbC002F6C-lbW002F5C ; 0
; dc.w lbC002F7E-lbW002F5C ; 2 read data
; dc.w lbC002FF4-lbW002F5C ; 4 write data
; dc.w lbC002F6C-lbW002F5C ; 6
;lbW002F64 dc.w lbC00307E-lbW002F64
; dc.w lbC00307E-lbW002F64
; dc.w lbC003072-lbW002F64
; dc.w lbC003072-lbW002F64
;lbC002F6C MOVE.B $1E-Modulo(A4),D0
; BTST #7,D0
; BNE.S lbC002F6C
;lbC002F76 MOVEQ #0,D0
;lbC002F78 MOVEM.L (SP)+,D2/D3
; RTS
;lbC002F7E MOVEA.L $60(A3),A1 ; read data (512 bytes)
; MOVEA.L A4,A0
; MOVE.L A1,D1
; BTST #0,D1
; BNE.S lbC002FD6
; MOVEQ #15,D0
;lbC002F8E MOVE.W (A0),(A1)+ ; even address copy routine
; MOVE.W (A0),(A1)+
; MOVE.W (A0),(A1)+
; MOVE.W (A0),(A1)+
; MOVE.W (A0),(A1)+
; MOVE.W (A0),(A1)+
; MOVE.W (A0),(A1)+
; MOVE.W (A0),(A1)+
; MOVE.W (A0),(A1)+
; MOVE.W (A0),(A1)+
; MOVE.W (A0),(A1)+
; MOVE.W (A0),(A1)+
; MOVE.W (A0),(A1)+
; MOVE.W (A0),(A1)+
; MOVE.W (A0),(A1)+
; MOVE.W (A0),(A1)+
; DBRA D0,lbC002F8E
;lbC002FB2 MOVE.L A1,$60(A3)
; MOVEA.L $6C(A3),A0
; ADDI.L #$200,8(A0)
; ADDQ.B #1,D3
; CMP.B $6C(A2),D3
; BCS.S lbC002FCC
; MOVEQ #0,D3
;lbC002FCC SUBQ.B #1,$4A(A3)
; BNE.W lbC002F18
; BRA.S lbC002F76
;lbC002FD6 MOVEQ #$7F,D0 ; odd address copy routine
;lbC002FD8 MOVE.W (A0),D1
; SWAP D1
; MOVE.W (A0),D1
; MOVE.B D1,3(A1)
; LSR.L #8,D1
; MOVE.W D1,1(A1)
; SWAP D1
; MOVE.B D1,(A1)
; ADDQ.W #4,A1
; DBRA D0,lbC002FD8
; BRA.S lbC002FB2
;lbC002FF4 MOVEA.L $60(A3),A1 ; write data (512 bytes)
; MOVEA.L A4,A0
; MOVE.L A1,D1
; BTST #0,D1
; BNE.S lbC003052
; MOVEQ #15,D0
;lbC003004 MOVE.W (A1)+,(A0) ; from even address
; MOVE.W (A1)+,(A0)
; MOVE.W (A1)+,(A0)
; MOVE.W (A1)+,(A0)
; MOVE.W (A1)+,(A0)
; MOVE.W (A1)+,(A0)
; MOVE.W (A1)+,(A0)
; MOVE.W (A1)+,(A0)
; MOVE.W (A1)+,(A0)
; MOVE.W (A1)+,(A0)
; MOVE.W (A1)+,(A0)
; MOVE.W (A1)+,(A0)
; MOVE.W (A1)+,(A0)
; MOVE.W (A1)+,(A0)
; MOVE.W (A1)+,(A0)
; MOVE.W (A1)+,(A0)
; DBRA D0,lbC003004
;lbC003028 MOVE.L A1,$60(A3)
; MOVEA.L $6C(A3),A0
; ADDI.L #$200,8(A0)
; ADDQ.B #1,D3
; CMP.B $6C(A2),D3
; BCS.S lbC003042
; MOVEQ #0,D3
;lbC003042 SUBQ.B #1,$4A(A3)
; BNE.W lbC002F18
; MOVEQ #0,D3
; MOVEQ #6,D2 ; 6 input
; BRA.W lbC002F18
;lbC003052 MOVEQ #$7F,D0 ; from odd address
;lbC003054 MOVE.B (A1),D1
; SWAP D1
; MOVE.W 1(A1),D1
; LSL.L #8,D1
; MOVE.B 3(A1),D1
; SWAP D1
; MOVE.W D1,(A0)
; SWAP D1
; MOVE.W D1,(A0)
; ADDQ.W #4,A1
; DBRA D0,lbC003054
; BRA.S lbC003028
;lbC003072 MOVEA.L $6C(A3),A0
; SUBI.L #$200,8(A0)
;lbC00307E BSR.S GetError
; BRA.W lbC002F78
;GetError BTST #6,$15(A2)
; BEQ.S lbC003092
; BSR.W lbC00231C ; why ? buggy call for me (wrong output)
; BRA.S lbC0030BE
;lbC003092 MOVE.B $16-Modulo(A4),D0
; LSL.W #8,D0
; MOVE.B $12-Modulo(A4),D0
; MOVE.W $5E(A2),D1
; MULU.W D0,D1
; MOVE.L D1,-(SP)
; MOVE.B $1A-Modulo(A4),D0
; AND.W #15,D0
; MOVEQ #0,D1
; MOVE.B $65(A2),D1
; MULU.W D0,D1
; ADD.L (SP)+,D1
; MOVE.B 14-Modulo(A4),D0
; SUBQ.B #1,D0
; ADD.L D0,D1
;lbC0030BE MOVE.L D1,$68(A2)
; MOVEQ #2,D0
; RTS
;lbC0030C6 MOVEA.L $68(A3),A1
; MOVE.B D0,(A1)
; RTS
; ReadWriteData (final version - 17 XII 2012)
; input D0
; output D0
; changed D0/D1/A0/A1
; input D0 = 0/2/4
; 0 = no data
; 2 = read command
; 4 = write command
ifne MC68000
OddWrite
moveq #$7F,D0 ; from odd address
LoopWO
move.l 1(A2),D1 ; 2/3/4/x
move.b (A2),D1 ; 2/3/4/1
rol.l #8,D1 ; 3/4/1/2
move.w D1,(A4)
swap D1
move.w D1,(A4)
addq.l #4,A2
dbf D0,LoopWO
bra.b BackW
endc
ReadWriteData
movem.l D2/D3/D4/D5/D6/A2,-(SP)
move.b $6C(A2),D4
move.l $60(A3),A2
move.b $4A(A3),D6
move.l $20(A5),D5
moveq #0,D2
subq.w #2,D0
beq.b GoR
subq.w #2,D0
beq.b GoW
bra.b QuitW
; WriteData routine
LoopW
subq.b #1,D6
beq.b QuitW
move.l D5,D0
jsr -$13E(A6) ; Wait
GoW
moveq #0,D3
WaitForReadyW
move.b $1E-Modulo(A4),D0
bmi.b WaitForReadyW
lsr.b #1,D0
bcs.b ErrorW
lsr.b #3,D0
bcc.b WaitForReadyW
ifne MC68000
move.l A2,D1
btst #0,D1
bne.b OddWrite
endc
moveq #15,D0
LoopWE
move.w (A2)+,(A4) ; from even address
move.w (A2)+,(A4)
move.w (A2)+,(A4)
move.w (A2)+,(A4)
move.w (A2)+,(A4)
move.w (A2)+,(A4)
move.w (A2)+,(A4)
move.w (A2)+,(A4)
move.w (A2)+,(A4)
move.w (A2)+,(A4)
move.w (A2)+,(A4)
move.w (A2)+,(A4)
move.w (A2)+,(A4)
move.w (A2)+,(A4)
move.w (A2)+,(A4)
move.w (A2)+,(A4)
dbf D0,LoopWE
BackW
addq.l #1,D2
addq.b #1,D3
cmp.b D4,D3
bcc.b LoopW
subq.b #1,D6
bne.b WaitForReadyW
QuitW
move.l D5,D0
jsr -$13E(A6) ; Wait
WaitW
move.b $1E-Modulo(A4),D0
bmi.b WaitW
bra.b QuitR
ErrorW
subq.l #1,D2
ErrorR
move.l A2,$60(A3)
move.l 20(SP),A2 ; restore A2
move.b 6-Modulo(A4),$277(A2)
bsr.b GetError
bra.b QuitE
; ReadData routine
LoopR
subq.b #1,D6
beq.b QuitR
GoR
moveq #0,D3
move.l D5,D0
jsr -$13E(A6) ; Wait
WaitForReadyR
move.b $1E-Modulo(A4),D0
bmi.b WaitForReadyR
lsr.b #1,D0
bcs.b ErrorR
lsr.b #3,D0
bcc.b WaitForReadyR
ifne MC68000
move.l A2,D1
btst #0,D1
bne.b OddRead
endc
moveq #15,D0
LoopRE
move.w (A4),(A2)+ ; even address copy routine
move.w (A4),(A2)+
move.w (A4),(A2)+
move.w (A4),(A2)+
move.w (A4),(A2)+
move.w (A4),(A2)+
move.w (A4),(A2)+
move.w (A4),(A2)+
move.w (A4),(A2)+
move.w (A4),(A2)+
move.w (A4),(A2)+
move.w (A4),(A2)+
move.w (A4),(A2)+
move.w (A4),(A2)+
move.w (A4),(A2)+
move.w (A4),(A2)+
dbf D0,LoopRE
BackR
addq.l #1,D2
addq.b #1,D3
cmp.b D4,D3
bcc.b LoopR
subq.b #1,D6
bne.b WaitForReadyR
QuitR
move.l A2,$60(A3)
moveq #0,D0 ; success
QuitE
move.l $6C(A3),A0
lsl.l #8,D2 ; *256
add.l D2,D2 ; *512
add.l D2,8(A0)
move.b D6,$4A(A3)
movem.l (SP)+,D2/D3/D4/D5/D6/A2
rts
ifne MC68000
OddRead
moveq #$7E,D0 ; odd address copy routine
LoopRO move.w (A4),D1
swap D1
move.w (A4),D1 ; 1/2/3/4
rol.l #8,D1 ; 2/3/4/1
move.b D1,(A2)+
move.l D1,(A2)
addq.l #3,A2
dbf D0,LoopRO
move.w (A4),D1 ; necessary due last byte is overwritten
swap D1
move.w (A4),D1 ; 1/2/3/4
rol.l #8,D1 ; 2/3/4/1
move.b D1,(A2)+
move.b 3(A2),D1 ; backup original byte value
move.l D1,(A2)
addq.l #3,A2
bra.b BackR
endc
GetError
btst #6,$15(A2)
beq.b CalcError
bsr.w lbC00231C
bra.b PutError
CalcError
move.b $16-Modulo(A4),D1
lsl.w #8,D1
move.b $12-Modulo(A4),D1
mulu.w $5E(A2),D1
moveq #15,D0
and.b $1A-Modulo(A4),D0
moveq #0,D3
move.b $65(A2),D3
mulu.w D0,D3
add.l D3,D1
move.b 14-Modulo(A4),D0
subq.b #1,D0
add.l D1,D0
PutError
move.l D0,$68(A2) ; here is my fix D1 replaced with D0
moveq #2,D0 ; error
rts