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After implementing the blitter in VHDL and studying the DMA sequences and the remarks from Toni, I think I get most of it :
- Sources A and B datapaths need two cycles to reach the minterm block because of the 32-bit shifter.
- Source C datapath needs just one cycle to reach the minterm block.
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I haven't thought about internal logic too much but this seems perfectly logical.
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I do not explain the fill mode "bug" yet, the only extra cycle that would make sense is for AD. It must be A, idle, D (if we suppose that the blitter needs an extra "fill mode" cycle after the "minterm" cycle occuring during A)
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I am quite sure it is AD- (A--AD-...AD--D)
(I guess the fill logic happens in "second cycle" in blitter pipeline)
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I bet it is 3 idle cycles if USEA=0 and 2 idle cycles if USEA=1.
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Yes. I meant 2 idle cycles that are always at start, not counting possible first "missing A" cycle. ("missing A" I counted as a part of "real" blitter cycle because it repeats)
EDIT: do you think 2 idle cycles at start are related to "preloading" A/B shifts or something?