Quote:
Originally Posted by Photon
I think this is a normal behavior of the vdu (IC) timing vs video timing. At least if I remember page 190 of HRM correctly.
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What chapter? Different HRM revisions have different page numbers
Perhaps it is documented somewhere but it has nothing to do with timing, Denise could simply inhibit sprite parallel to serial conventers after DDFSTOP but I am quite sure Denise does not know anything about DDFSTRT or DDFSTOP, it most likely waits for first BPL1DAT write (by Agnus) which then starts display processing circuitry until next hsync.