Quote:
Originally Posted by PiCiJi
In both situations?
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If by "both situations" do you mean the two 'temporal positions' where BLTCON0 can be written, then yes, that's how it seems.
(there is actually only one situation, the (re)write with active blitter of different number of channels, in two possible different internal blitter shifter conditions).
The difference at the 'change start' is this:
- A BLTCON0 DACC-ACCC
- D BLTCON0 ADAC-CCAC
I can double check but I've only ever seen ACCC.
But there is a difference when counter expires (i.e. last full cycle):
- CCCACCCD-D
- ACCCABCD-D
Interesting, right?
Don't ask me for more details because other in-depth tests need to be done
But the fix made by Toni works perfectly for the current case and previous similar cases.