Quote:
Originally Posted by Gorf
With 70ns FPM on board double CAS should be possible for these operations, meaning Gary would take 32-bit from/to CPU and make two consecutive 16-bit writes/reads on ChipRam... no?
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If Gary is altered to signal that chip RAM is 16-bit then I'm not sure if the MUXes will work right. Might need to check. If it can work then the 3000 would have as slow access to chip as all other ECS machines.
Yes, with 70ns RAM, burst mode might have been available, but I'm pretty sure Gary lacks the signalling to the CPU to make that work. 70ns RAM might (just) fast enough to theoretically squeeze in two regular read operations (120ns) in the Agnus allocated interleave but that's pushing it. But may be possible. I think there's timing on top of that 120ns on the CPU side that might blow over the 140ns budget without a really fast 030.