This post is mostly about boring DRAM refresh (DRAM refresh basic information required. For example check Wikipedia "Memory refresh" article).
Normally this should be completely invisible to programmer and user but "unfortunately" memory refresh behavior becomes visible if bitplane DMA conflicts with refresh slots.
Agnus/Alice handles Chip RAM refresh, they have hidden undocumented internal refresh DMA pointer (Shortened "RDMAPT"). It is not row-only refresh counter, it is full DMA pointer (like any other "normal" DMA pointer). All chipsets except AGA increase refresh pointer after each refresh slot. OCS increases it by one but ECS increases it by $100 ($200 from programmer's point of view). RDMAPT to row/column Chip DRAM addressing "wiring" changed in ECS. Externally this always increases row (RAS) by one.
REFPTR can be used to modify internal RDMAPT but because REFPTR is only 16-bits (probably because chip ram size was only 128k in original Amiga chipset design = 65536 16-bit words), single REFPTR bit can modify 2 RDMAPT bits in later chipsets. (Detailed in attached diagrams). This register was most likely used for chip testing/validation because it also sets column part of address which is not needed during refresh cycles. (But it is very nice that both row and column addresses are always generated externally because it helped to decode the behavior of both row/column/RAS/CAS signals and RDMAPT adder logic)
Refresh slots work almost like any other normal DMA slot, RDMAPT value is output to external Chip RAM address bus (first row, then column) but data is not transferred and RAS/CAS signals generate DRAM refresh cycle. Column address is also generated during refresh cycles which gets ignored by DRAM chips.
Bitplane conflict with refresh slot behavior details will be explained in future post.
Chipset differences:
Code:
System | RAS/CAS | Refresh | Max Chip | Notes
-------------------------------------------------------
Velvet| 8 + 8 | ROR 8 | 128k | Not confirmed.
A1000 | 9 + 9 | ROR 8 | 512k | External RAS/CAS circuitry, number of address lines increased by 1.
OCS | 9 + 9 | ROR 8 | 512k | RAS/CAS Agnus internal, 2xRAS pins (second used for trapdoor addressing)
1M ECS | [9+1] + 9 | ROR 9 | 1024k | 9-bit refresh, 4x256k DRAM chip support.
2M ECS | [9+1] + [9+1] | ROR 9 | 2048k | Number of address lines increased by 1.
AGA | 10 + 10 | CBR - | 2048k | RDMAPT still exists but it is not incremented anymore.
| Only 1 RAS and CAS signal (Budgie generates others)
ROR 8 = RAS only refresh, 8 bit row refresh counter.
ROR 9 = RAS only refresh, 9 bit row refresh counter.
CBR = CAS before RAS refresh. DRAM internal refresh counter.
See attached diagrams for details. Diagrams and lots of weird test programs by Ross.
(Yes, all this, and more that is detailed in later post, needs to be emulated to have mostly useless fully accurate corrupted output when program has bitplane to refresh slot conflicts..)